The DMD HV regulator, DMD buck converters, auxiliary LDOS and the LDO DMD that supports the HV regulator have a power good indication.

The DMD HV regulator is continuously monitored to check if the output rails DMD_VRESET, DMD_VOFFSET and DMD_VBIAS are in regulation. If either one of the output rails drops out of regulation (for example, due to a shorted output or overloading), the DMD_ PG_FAULT bit in Detailed Status Register3 (0x29) is set. The threshold for DMD_VRESET is 90% and the thresholds for DMD_VOFFSET and DMD_VBIAS are 86% (rising edge) and 66% (falling edge).

The power good signal for the two DMD buck converters indicate if their output voltage (PWR1_FB and PWR2_FB) are within a defined window. The relative power good ratio is 72%. This means that if the output voltage is below 72% of the set output voltage, the power good bit is asserted. The power good bits are in Detailed Status Register3 (0x29), bits BUCK_DMD1_PG_FAULT and BUCK_DMD2_PG_FAULT.

LDO_1 and LDO_2 output voltages are also monitored. When the power good fault of the LDO is asserted, it implies that the LDO voltage is below 80% (rising edge) or 60% (falling edge) of its intended value. The power good indication for the LDOs is in Detailed Status Register3 (0x29) , bits LDO_GP1_PG_FAULT / LDO_DMD1_PG_FAULT and LDO_GP2_PG_FAULT / LDO_DMD2_PG_FAULT.