ZHCSE87A October   2015  – September 2023 DLPA3000

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Revision History
  6. 说明(续)
  7. Pin Configuration and Functions
  8. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Parameters
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 功能方框图
    3. 8.3 Feature Description
      1. 8.3.1 Supply and Monitoring
        1. 8.3.1.1 Supply
        2. 8.3.1.2 Monitoring
          1. 8.3.1.2.1 Block Faults
          2. 8.3.1.2.2 Low Battery and UVLO
          3. 8.3.1.2.3 Auto LED Turn Off Functionality
          4. 8.3.1.2.4 Thermal Protection
      2. 8.3.2 Illumination
        1. 8.3.2.1 Programmable Gain Block
        2. 8.3.2.2 LDO Illum
        3. 8.3.2.3 Illumination Driver A
        4. 8.3.2.4 RGB Strobe Decoder
          1. 8.3.2.4.1 Break Before Make (BBM)
          2. 8.3.2.4.2 Openloop Voltage
          3. 8.3.2.4.3 Transient Current Limit
        5. 8.3.2.5 Illumination Monitoring
          1. 8.3.2.5.1 Power Good
          2. 8.3.2.5.2 Ratio Metric Overvoltage Protection
        6. 8.3.2.6 Load Current and Supply Voltage
        7. 8.3.2.7 Illumination Driver Plus Power FETS Efficiency
      3. 8.3.3 DMD Supplies
        1. 8.3.3.1 LDO DMD
        2. 8.3.3.2 DMD HV Regulator
          1. 8.3.3.2.1 Power-Up and Power-Down Timing
        3. 8.3.3.3 DMD/DLPC Buck Converters
        4. 8.3.3.4 DMD Monitoring
          1. 8.3.3.4.1 Power Good
          2. 8.3.3.4.2 Overvoltage Fault
      4. 8.3.4 Buck Converters
        1. 8.3.4.1 LDO Bucks
        2. 8.3.4.2 General Purpose Buck Converters
        3. 8.3.4.3 Buck Converter Monitoring
          1. 8.3.4.3.1 Power Good
          2. 8.3.4.3.2 Overvoltage Fault
        4. 8.3.4.4 Buck Converter Efficiency
      5. 8.3.5 Auxiliary LDOs
      6. 8.3.6 Measurement System
      7. 8.3.7 Digital Control
        1. 8.3.7.1 SPI
        2. 8.3.7.2 Interrupt
        3. 8.3.7.3 Fast-Shutdown in Case of Fault
    4. 8.4 Device Functional Modes
    5. 8.5 Register Maps
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Typical Application Setup Using DLPA3000
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Typical Application with DLPA3000 Internal Block Diagram
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 SPI Connections
    4. 11.4 RLIM Routing
    5. 11.5 LED Connection
    6. 11.6 Thermal Considerations
  13. 12Device and Documentation Support
    1. 12.1 第三方米6体育平台手机版_好二三四免责声明
    2. 12.2 Device Support
      1. 12.2.1 Device Nomenclature
    3. 12.3 Related Links
    4. 12.4 接收文档更新通知
    5. 12.5 支持资源
    6. 12.6 Trademarks
    7. 12.7 支持资源
    8. 12.8 静电放电警告
    9. 12.9 术语表
  14. 13Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

Supply

SYSPWR is the main supply of the DLPA3000. It can range from 6 V to 20 V, where the typical is 12 V. At power-up, several (internal) power supplies are started one after the other to make the system work correctly (Figure 8-1). A sequential startup provides that all the different blocks start in a certain order and prevent excessive startup currents. The main control to start the DLPA3000 is the control pin PROJ_ON. Once set high, the basic analog circuitry is started, which is needed to operate the digital and SPI interface. This circuitry is supplied by two LDO regulators that generate 2.5 V (SUP_2P5V) and 5 V (SUP_5P0V). These regulator voltages are for internal use only and not loaded by an external application. The output capacitors of those LDOs must be 2.2 µF for the 2.5 V LDO and 4.7 µF for the 5 V LDO, pin 91 and 92, respectively. Once these are up the digital core is started, and the DLPA3000 Digital State Machine (DSM) takes over.

Subsequently, the 5.5 V LDOs for various blocks are started: PWR_5V5V, DRST_5P5V and ILLUM_5P5V. Next, the buck converters and DMD LDOs are started (PWR_1 to PWR_4). The DLPA3000 is now awake and ready to be controlled by the DLPC (indicated by RESET_Z going high).

Lastly, the general purpose buck converters (PWR_6) can be started (if used) as well as the regulator that supplies the DMD. The DMD regulator generates the timing critical VOFFSET, VBIAS, and VRESET supplies.

GUID-20230612-SS0I-6G2V-M0PH-HRRQF0FBNK8L-low.gif
  1. Arrows indicate sequence of events automatically controlled by digital state machine. Other events are initiated under SPI control.
  2. SUP_5P0V and SUP_2P5V rise to a precharge level with SYSPWR, and reach the full level potential after PROJ_ON is pulled high.
Figure 8-1 Powerup Timing