米6体育平台手机版

ZHCSE88A October 2015 – February 2023 DLPA3005

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

PFD|100
- MPQF054B

散热焊盘机械数据 (封装 | 引脚)

PFD|100
- PPTD321

订购信息

zhcse88a_oa

6.5 Electrical Characteristics

Over operating free-air temperature range. V_IN = 12 V, T_A = 0 to +70°C, typical values are at T_A = 25°C, Configuration according to GUID-197A57DC-5404-4EC1-84CE-DC857D72222E.html#GUID-197A57DC-5404-4EC1-84CE-DC857D72222E (V_IN =12 V, I_OUT = 16 A, LED, external FETs) (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLIES
INPUT VOLTAGE
V_IN	Input voltage range	VINA – pin	6⁽⁶⁾	12	20	V
V_UVLO⁽⁷⁾	UVLO threshold	VINA falling (through a 5-bit trim function, 0.5-V steps)	3.9	6.22	18.4	V
V_UVLO⁽⁷⁾	Hysteresis	VINA rising		90		mV
V_STARTUP	Startup voltage	DMD_VBIAS, DMD_VOFFSET, DMD_VRESET loaded with 10 mA	6			V
INPUT CURRENT
I_IDLE	Idle current	IDLE mode, all VIN pins combined		15		µA
I_STD	Standby current	STANDBY mode, analog, internal supplies and LDOs enabled, DMD, ILLUMINATION and BUCK CONVERTERS disabled.		3.7		mA
I_{Q_DMD}	Quiescent current (DMD)	Quiescent current DMD block (in addition to I_STD), VINA + DRST_VIN		0.49		mA
I_{Q_ILLUM}	Quiescent current (ILLUM)	Quiescent current ILLUM block (in addition to I_STD), V_openloop= 3 V (ILLUM_OLV_SEL), VINA + ILLUM_VIN + ILLUM_A_VIN + ILLUM_B_VIN		21		mA
I_{Q_BUCK}	Quiescent current (per BUCK)	Quiescent current per BUCK converter (in addition to I_STD), Normal mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN, PWR1,2,5,6,7_VOUT = 1 V		4.3		mA
		Quiescent current per BUCK converter (in addition to I_STD), Normal mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN, PWR1,2,5,6,7_VOUT = 5 V		15
		Quiescent current per BUCK converter (in addition to I_STD), Cycle-skipping mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN = 1 V		0.41
		Quiescent current per BUCK converter (in addition to I_STD), Cycle-skipping mode, VINA + PWR_VIN + PWR1,2,5,6,7_VIN = 5 V		0.46
I_{Q_TOTAL}	Quiescent current (Total)	Typical Application: ACTIVE mode, all VIN pins combined, DMD, ILLUMINATION and PWR1,2 enabled, PWR3,4,5,6,7 disabled.		38		mA
INTERNAL SUPPLIES
V_{SUP_5P0V}	Internal supply, analog			5		V
V_{SUP_2P5V}	Internal supply, logic			2.5		V
DMD—LDO DMD
V_{DRST_VIN}			6	12	20	V
V_{DRST_5P5V}				5.5		V
PGOOD	Power good DRST_5P5V	Rising		80%
PGOOD	Power good DRST_5P5V	Falling		60%
OVP	Overvoltage protection DRST_5P5V			7.2		V
	Regulator dropout	At 25 mA, VDRST_VIN= 5.5 V		56		mV
	Regulator current limit⁽²⁾		300	340	400	mA
DMD—REGULATOR
R_DS(ON)	MOSFET ON-resistance	Switch A (from DRST_5P5V to DRST_HS_IND)		920		mΩ
R_DS(ON)	MOSFET ON-resistance	Switch B (from DRST_LS_IND to DRST_PGND)		450		mΩ
V_FW	Forward voltage drop	Switch C (from DRST_LS_IND to DRST_VBIAS⁽¹⁾), VDRST_LS_IND = 2 V, I_F = 100 mA		1.21		V
V_FW	Forward voltage drop	Switch D (from DRST_LS_IND to DRST_VOFFSET⁽¹⁾), VDRST_LS_IND = 2 V, I_F = 100 mA		1.22		V
t_DIS	Rail Discharge time	C_OUT = 1 µF			40	µs
t_PG	Power-good timeout	Not tested in production		15		ms
I_LIMIT	Switch current limit			610		mA
VOFFSET REGULATOR
V_OFFSET	Output voltage			10		V
	DC output voltage accuracy	I_OUT = 10 mA	-0.3		0.3	V
	DC Load regulation	I_OUT = 0 mA to 10 mA		–10		V/A
	DC Line regulation	I_OUT = 10 mA, DRST_VIN = 8 V to 20 V		–5		mV/V
V_RIPPLE	Output ripple	I_OUT = 10 mA, C_OUT= 1 µF		200		mVpp
I_OUT	Output current		0.1		10	mA
PGOOD	Power-good threshold (fraction of nominal output voltage)	VOFFSET rising		86%
PGOOD	Power-good threshold (fraction of nominal output voltage)	VOFFSET falling		66%
C	Output capacitor	Recommended value⁽⁵⁾ (use same value as output capacitor on VRESET)	1			µF
C	Output capacitor	t_DISCHARGE <40 µs at VIN = 8 V			1	µF
VBIAS REGULATOR
V_BIAS	Output voltage			18		V
	DC output voltage accuracy	I_OUT = 10 mA	–0.3		0.3	V
	DC Load regulation	I_OUT = 0 to 10 mA		–18		V/A
	DC Line regulation	I_OUT = 10 mA, DRST_VIN = 8 V to 20 V		–3		mV/V
V_RIPPLE	Output ripple	I_OUT = 10 mA, C_OUT= 470 nF		200		mVpp
I_OUT	Output current		0.1		10	mA
PGOOD	Power-good threshold (fraction of nominal output voltage)	VBIAS rising		86%
PGOOD	Power-good threshold (fraction of nominal output voltage)	VBIAS falling		66%
C	Output capacitor	Recommended value⁽⁵⁾ (use same or smaller value as output capacitors VOFFSET / VRESET)	470			nF
C	Output capacitor	t_DISCHARGE <40 µs at VIN = 8 V			470	nF
VRESET REGULATOR
V_RST	Output voltage			–14		V
	DC output voltage accuracy	I_OUT = 10 mA	-0.3		0.3	V
	DC Load regulation	I_OUT = 0 to 10 mA		–4		V/A
	DC Line regulation	I_OUT = 10 mA, DRST_VIN = 8 to 20 V		–2		mV/V
V_RIPPLE	Output ripple	I_OUT = 10 mA, C_OUT = 1 µF		120		mVpp
I_OUT	Output current		0.1		10	mA
PGOOD	Power-good threshold			90%
C	Output capacitor	Recommended value⁽⁵⁾ (use same value as output capacitor on VOFFSET)	1			µF
C	Output capacitor	t_DISCHARGE <40 µs at VIN = 8 V			1	µF
DMD - BUCK CONVERTERS
OUTPUT VOLTAGE
V_{PWR_1_VOUT}	Output Voltage			1.1		V
V_{PWR_2_VOUT}	Output Voltage			1.8		V
	DC output voltage accuracy	I_OUT= 0 mA	–3%		3%
MOSFET
R_ON,H	High side switch resistance	25°C, V_{PWR_1,2_Boost} – V_{PWR1,2_SWITCH} = 5.5 V		150		mΩ
R_ON,L	Low side switch resistance⁽²⁾	25°C		85		mΩ
LOAD CURRENT
	Allowed Load Current⁽³⁾.				3	A
I_OCL	Current limit⁽²⁾	L_OUT= 3.3 μH	3.2	3.6	4.2	A
ON-TIME TIMER CONTROL
t_ON	On time	V_IN = 12 V, V_O = 5 V		120		ns
t_OFF(MIN)	Minimum off time⁽²⁾	T_A = 25°C, V_FB = 0 V		270		ns
START-UP
	Soft start		1	2.5	4	ms
PGOOD
Ratio_OV	Overvoltage protection			120%
Ratio_PG	Relative power good level	Low to high		72%
ILLUMINATION—LDO ILLUM
V_{ILLUM_VIN}			6	12	20	V
V_{ILLUM_5P5V}				5.5		V
PGOOD	Power good ILLUM_5P5V	Rising		80%
PGOOD	Power good ILLUM_5P5V	Falling		60%
OVP	Overvoltage protection ILLUM_5P5V			7.2		V
	Regulator dropout	At 25 mA, V_{ILLUM_VIN} = 5.5 V		53		mV
	Regulator current limit⁽²⁾		300	340	400	mA
ILLUMINATION—DRIVER A,B
V_{ILLUM_A,B_IN}	Input supply voltage range		6	12	20	V
PWM
ƒ_SW	Oscillator frequency	3 V < V_IN < 20 V		600		kHz
t_DEAD	Output driver dead time	HDRV off to LDRV on, TRDLY = 0		28		ns
		HDRV off to LDRV on, TRDLY = 1		40
		LDRV off to HDRV on, TRDLY = 0		35
OUTPUT DRIVERS
R_HDHI	High-side driver pull-up resistance	V_{ILLUM_A,B_BOOT} – V_{ILLUM_A,B_SW} = 5 V, I_HDRV = –100 mA		4.9		Ω
R_HDLO	High-side driver pull-down resistance	V_{ILLUM_A,B_BOOT} – V_{ILLUM_A,B_SW} = 5 V, I_HDRV = 100 mA		3		Ω
R_LDHI	Low-side driver pull-up resistance	I_LDRV = –100 mA		3.1		Ω
R_LDLO	Low-side driver pull-down resistance	I_LDRV = 100 mA		2.4		Ω
t_HRISE	High-side driver rise time⁽²⁾	C_LOAD = 5 nF		23		ns
t_HFALL	High-side driver fall time⁽²⁾	C_LOAD = 5 nF		19		ns
t_LRISE	Low-side driver rise time⁽²⁾	C_LOAD = 5 nF		23		ns
t_LFALL	Low-side driver fall time⁽²⁾	C_LOAD = 5 nF		17		ns
OVERCURRENT PROTECTION
HSD OC	High-Side Drive Over Current threshold	External switches, V_DS threshold⁽²⁾		185		mV
BOOT DIODE
V_DFWD	Bootstrap diode forward voltage	I_BOOT = 5 mA		0.75		V
PGOOD
RatioUV	Undervoltage protection			89%
DRIVERS EXTERNAL RGB STROBE CONTROLLER SWITCHES
CHx_GATE_CNTR_HIGH	Gate control high level	ILLUM_SW_ILIM_EN[2:0] = 7, register 0x02, I_SINK= 400 µA		4.35		V
CHx_GATE_CNTR_HIGH	Gate control high level	ILLUM_SW_ILIM_EN[2:0] = 0, register 0x02, I_SINK= 400 µA		5.25		V
CHx_GATE_CNTR_LOW	Gate control low level	ILLUM_SW_ILIM_EN[2:0] = 7, register 0x02, I_SINK= 400 µA		55		mV
CHx_GATE_CNTR_LOW	Gate control low level	ILLUM_SW_ILIM_EN[2:0] = 0, register 0x02, I_SINK= 400 µA		55		mV
LED CURRENT CONTROL
V_{LED_ANODE}	LED Anode voltage⁽²⁾	Ratio with respect to V_{ILLUM_A,B_VIN} (Duty cycle limitation).	0.85x
V_{LED_ANODE}	LED Anode voltage⁽²⁾				15.5	V
I_LED	LED currents	V_{ILLUM_A,B_VIN} ≥ 8 V. See register SWx_IDAC[9:0] for settings.	1		16⁽⁹⁾	A
	DC current offset, CH1,2,3_SWITCH	R_LIM = 12.5 mΩ	–150	0	150	mA
	Transient LED current limit range (programmable)	20% higher than I_LED. Min-setting, R_LIM= 12.5 mΩ		11%
	Transient LED current limit range (programmable)	20% higher than I_LED. Max-setting, R_LIM= 12.5 mΩ. Percentage of max current		133%
t_RISE	Current rise time	I_LED from 5% to 95%, I_LED = 600 mA, transient current limit disabled⁽²⁾			50	µs
BUCK CONVERTERS—LDO_BUCKS
V_{PWR_VIN}	Input voltage range PWR1,2,5,6,7_VIN		6	12	20	V
V_{PWR_5P5V}	PWR_5P5V			5.5		V
PGOOD	Power good PWR_5P5V	Rising		80%
PGOOD	Power good PWR_5P5V	Falling		60%
OVP	Overvoltage Protection PWR_5P5V			7.2		V
	Regulator dropout	At 25 mA, V_{PWR_VIN}= 5.5 V		41		mV
	Regulator current limit⁽²⁾		300	340	400	mA
BUCK CONVERTER - GENERAL PURPOSE BUCK CONVERTER ⁽⁸⁾
OUTPUT VOLTAGE
V_{PWR_6_VOUT}	Output Voltage (General Purpose Buck2)	8-bit programmable	1		5	V
	DC output voltage accuracy	I_OUT= 0 mA	–3.5%		3.5%
MOSFET
R_ON,H	High side switch resistance	25°C, V_{PWR6_Boost} – V_{PWR6_SWITCH} = 5.5 V		150		mΩ
R_ON,L	Low side switch resistance⁽²⁾	25°C		85		mΩ
LOAD CURRENT
	Allowed Load Current PWR6⁽³⁾.			2		A
I_OCL	Current limit⁽²⁾⁽³⁾	L_OUT= 3.3 μH	3.2	3.6	4.2	A
ON-TIME TIMER CONTROL
t_ON	On time	V_IN = 12 V, V_O = 5 V		120		ns
t_OFF(MIN)	Minimum off time⁽²⁾	T_A = 25°C, V_FB = 0 V		270	310	ns
START-UP
	Soft start		1	2.5	4	ms
PGOOD
Ratio_OV	Overvoltage protection			120%
Ratio_PG	Relative power good level	Low to high		72%
AUXILIARY LDOs
V_{PWR3,4_VIN}	Input voltage range	LDO1 (PWR4), LDO2 (PWR3)	3.3	12	20	V
PGOOD	Power good PWR3,4_VOUT	PWR3,4_VOUT rising		80%
		PWR3,4_VOUT falling		60%
OVP	Overvoltage Protection PWR3,4_VOUT			7		V
	DC output voltage accuracy PWR3,4_VOUT	I_OUT= 0 mA	–3%		3%
	Regulator current limit⁽²⁾		300	340	400	mA
t_ON	Turn-on time	to 80% of V_OUT = PWR3 and PWR4, C= 1 µF		40		µs
LDO2 (PWR3)
V_{PWR3_VOUT}	Output Voltage PWR3_VOUT			2.5		V
	Load Current capability			200		mA
	DC Load regulation PWR3_VOUT	V_OUT= 2.5 V, I_OUT= 5 to 200 mA		–70		mV/A
	DC Line regulation PWR3_VOUT	V_OUT= 2.5 V, I_OUT= 5 mA, PWR3_VIN = 3.3 to 20 V		30		µV/V
LDO1 (PWR4)
V_{PWR4_VOUT}	Output Voltage PWR4_VOUT			3.3		V
	Load Current capability			200		mA
	DC Load regulation PWR4_VOUT	V_OUT= 3.3 V, I_OUT= 5 to 200 mA		–70		mV/A
	DC Line regulation PWR4_VOUT	V_OUT= 3.3V, I_OUT= 5 mA, PWR4_VIN= 4 to 20 V		30		µV/V
	Regulator dropout	At 25 mA, V_OUT= 3.3 V, V_{PWR4_VIN}= 3.3 V		48		mV
MEASUREMENT SYSTEM
LABB
τ_RC	Settling time	To 1% of final value⁽²⁾		4.6	6.6	µs
τ_RC	Settling time	To 0.1% of final value⁽²⁾		7	10	µs
V_{ACMPR_IN_LABB}	Input voltage range ACMPR_IN_LABB		0		1.5	V
	Sampling window ACMPR_IN_LABB	Programmable per 7 µs	7		28	µs
DIGITAL CONTROL - LOGIC LEVELS AND TIMING CHARACTERISTICS
V_{SPI_VIN}	SPI supply voltage range	SPI_VIN	1.7		3.6	V
V_OL	Output low-level	RESET_Z, ACMPR_OUT, CLK_OUT. I_O = 0.3 mA sink current	0		0.3	V
		SPI_DOUT. I_O = 5 mA sink current	0		0.3 × V_{SPI_VIN}
		INT_Z. I_O = 1.5 mA sink current	0		0.3 × V_{SPI_VIN}
V_OH	Output high-level	RESET_Z, ACMPR_OUT, CLK_OUT. I_O = 0.3 mA source current	1.3		2.5	V
V_OH	Output high-level	SPI_DOUT. I_O = 5 mA source current	0.7 × V_{SPI_VIN}		V_{SPI_VIN}	V
V_IL	Input low-level	PROJ_ON, CH_SEL_0, CH_SEL_1	0		0.4	V
V_IL	Input low-level	SPI_CSZ, SPI_CLK, SPI_DIN	0		0.3 × V_{SPI_VIN}	V
V_IH	Input high-level	PROJ_ON, CH_SEL_0, CH_SEL_1	1.2			V
V_IH	Input high-level	SPI_CSZ, SPI_CLK, SPI_DIN	0.7 × V_{SPI_VIN}		V_{SPI_VIN}	V
I_BIAS	Input bias current	V_IO= 3.3 V, any digital input pin			0.1	µA
SPI_CLK	SPI clock frequency⁽⁴⁾	Normal SPI mode, DIG_SPI_FAST_SEL = 0, ƒ_OSC = 9 MHz	0		36	MHz
SPI_CLK	SPI clock frequency⁽⁴⁾	Fast SPI mode, DIG_SPI_FAST_SEL = 1, V_{SPI_VIN}> 2.3 V, ƒ_OSC = 9 MHz	20		40	MHz
t_DEGLITCH	Deglitch time	CH_SEL_0, CH_SEL_1⁽²⁾		300		ns
INTERNAL OSCILLATOR
ƒ_OSC	Oscillator frequency			9		MHz
	Frequency accuracy	T_A= 0 °C to 70°C	–5%		5%
THERMAL SHUTDOWN
T_WARN	Thermal warning (HOT threshold)			120		°C
T_WARN	Hysteresis			10		°C
T_SHTDWN	Thermal shutdown (TSD threshold)			150		°C
T_SHTDWN	Hysteresis			15		°C

(1) Including rectifying diode

(2) Not production tested

(3) Care should be taken not to exceed the max power dissipation. Refer to GUID-5875BE2B-5903-470C-9454-84171946BB9C.html#GUID-5875BE2B-5903-470C-9454-84171946BB9C.

(4) Maximum depends linearly on oscillator frequency f_OSC.

(5) Take care that the capacitor has the specified capacitance at the related voltage, that is, V_OFFSET, V_BIAS, or V_RESET.

(6) VIN must be higher than the UVLO voltage setting, including after accounting for AC noise on VIN, for the DLPA3005 to fully operate. While 6.0 V is the min VIN voltage supported, TI recommends that the UVLO is never set below 6.21 V for fault fast power down. 6.21 V gives margin above 6.0 V to protect against the case where someone suddenly removes VIN’s power supply which causes the VIN voltage to drop rapidly. Failure to keep VIN above 6.0V before the mirrors are parked and VOFS, VRST, and VBIAS supplies are properly shut down can result in permanent damage to the DMD. Since 6.21 V is .21 V above 6.0 V, when UVLO trips there is time for the DLPA3005 and DLPC343x to park the DMD mirrors and do a fast shut down of supplies VOFS, VRST, and VBIAS. For whatever UVLO setting is used, if VIN’s power supply is suddenly removed enough bulk capacitance should be included on VIN inside the projector to keep VIN above 6.0V for at least 100us after UVLO trips.

(7) UVLO should not be used for normal power down operation, it is meant as a protection from power loss.

(8) General purpose buck2 (PWR6) is currently supported.

(9) Supports up to 32 A for series LEDs based on reference hardware design.