米6体育平台手机版

ZHCSDJ3C March 2015 – June 2019 DLPC150

PRODUCTION DATA.

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ZEZ|201
- MPBGAK7

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6.12 Parallel Interface General Timing Requirements⁽²⁾

			MIN	MAX	UNIT
ƒ_clock	Clock frequency, PCLK		1	75	MHz
t_{p_clkper}	Clock period, PCLK	50% reference points	6.66	1000	ns
t_{p_clkjit}	Clock jitter, PCLK	Max ƒ_clock	see ⁽¹⁾	see ⁽¹⁾
t_{p_wh}	Pulse duration low, PCLK	50% reference points	2.43		ns
t_{p_wl}	Pulse duration high, PCLK	50% reference points	2.43		ns
t_{p_su}	Setup time – HSYNC_CS, DATEN_CMD, PDATA(23:0) valid before the active edge of PCLK	50% reference points	0.9		ns
t_{p_h}	Hold time – HSYNC_CS, DATEN_CMD, PDATA(23:0) valid after the active edge of PCLK	50% reference points	0.9		ns
t_t	Transition time – all signals	20% to 80% reference points	0.2	2	ns

(1) Clock jitter (in ns) should be calculated using this formula: Jitter = [1 / ƒ_clock – 5.76 ns]. Setup and hold times must be met during clock jitter.

(2) The active (capture) edge of PCLK for HSYNC_CS, DATEN_CMD and PDATA(23:0) is software programmable, but defaults to the rising edge.

Figure 6. Parallel Interface General Timing

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6.12 Parallel Interface General Timing Requirements(2)

6.12 Parallel Interface General Timing Requirements⁽²⁾