ZHCSDJ3C March 2015 – June 2019 DLPC150
PRODUCTION DATA.
- 1 特性
- 2 应用
- 3 说明
- 4 修订历史记录
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics Over Recommended Operating Conditions
- 6.6 Electrical Characteristics
- 6.7 High-Speed Sub-LVDS Electrical Characteristics
- 6.8 Low-Speed SDR Electrical Characteristics
- 6.9 System Oscillators Timing Requirements
- 6.10 Power-Up and Reset Timing Requirements
- 6.11 Parallel Interface Frame Timing Requirements
- 6.12 Parallel Interface General Timing Requirements
- 6.13 Flash Interface Timing Requirements
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
-
11Layout
- 11.1
Layout Guidelines
- 11.1.1 PCB Layout Guidelines For Internal Controller PLL Power
- 11.1.2 DLPC150 Reference Clock
- 11.1.3 General PCB Recommendations
- 11.1.4 General Handling Guidelines for Unused CMOS-Type Pins
- 11.1.5 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
- 11.1.6 Number of Layer Changes
- 11.1.7 Stubs
- 11.1.8 Terminations
- 11.1.9 Routing Vias
- 11.2 Layout Example
- 11.3 Thermal Considerations
- 11.1
Layout Guidelines
- 12器件和文档支持
- 13"机械、封装和可订购信息
8.3.7 DMD Interface Considerations
The sub-LVDS HS interface waveform quality and timing on the DLPC150 controller is dependent on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.
As an example, DMD interface system timing margin can be calculated as follows:
where
DLPC150 I/O timing parameters as well as DMD I/O timing parameters can be found in their corresponding data sheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. However, PCB SI degradation is a more complicated adjustment.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design guidelines are provided as a reference of an interconnect system that will satisfy both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements.
| DMD_HS Differential Signals | DMD_LS Signals |