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ZHCSDJ3C March 2015 – June 2019 DLPC150

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

ZEZ|201
- MPBGAK7

散热焊盘机械数据 (封装 | 引脚)

5 Pin Configuration and Functions

ZEZ Package

201-Pin VFBGA

Bottom View

Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NAME	NO.	I/O⁽¹⁾	DESCRIPTION
CONTROL AND INITIALIZATION
RESETZ	C11	I₆	DLPC150 power-on reset (active low input) (hysteresis buffer). Self-configuration starts when a low-to-high transition is detected on RESETZ. All DLPC150 controller power and clocks must be stable before this reset is de-asserted. Connect to the reset output pin (RESETZ) of the DLPA2000 or DLPA2005 PMIC. Note that the following signals will be tri-stated while RESETZ is asserted: SPI0_CLK, SPI0_DOUT, SPI0_CSZ0, SPI0_CSZ1, PMIC_SPI_CLK, PMIC_SPI_CSZ, PMIC_SPI_DIN, PMIC_SPI_DOUT, TRIG_OUT_1, TRIG_OUT_2, and GPIO[19:05] External pullups or downs (as appropriate) should be added to all tri-stated output signals listed (including bidirectional signals to be configured as outputs) to avoid floating DLPC150 controller outputs during reset if connected to devices on the PCB that can malfunction. For SPI, at a minimum, any chip selects connected to the devices should have a pullup. Unused bidirectional signals can be functionally configured as outputs to avoid floating DLPC150 controller inputs after RESETZ is set high. The following signals are forced to a logic low state while RESETZ is asserted and corresponding I/O power is applied: LED_SEL_0, LED_SEL_1 and DMD_DEN_ARSTZ No signals will be in their active state while RESETZ is asserted. Note that no I²C activity is permitted for a minimum of 500 ms after RESETZ (and PARKZ) are set high.
PARKZ	C13	I₆	DMD fast PARK control (active low Input) (hysteresis buffer). PARKZ must be set high to enable normal operation. PARKZ should be set high prior to releasing RESETZ (that is, prior to the low-to-high transition on the RESETZ input). PARKZ should be set low for a minimum of 40 µs before any power is removed from the DLPC150 such that the fast DMD PARK operation can be completed. Note for PARKZ, fast PARK control should only be used when loss of power is eminent and beyond the control of the host processor (for example, when the external power source has been disconnected or the battery has dropped below a minimum level). The longest lifetime of the DMD may not be achieved with the fast PARK operation. The longest lifetime is achieved with a normal PARK operation. Because of this, PARKZ is typically used in conjunction with a normal PARK request control input through PROJ_ON. The difference being that when the host sets PROJ_ON low, which connects to both DLPC150 and the DLPA200x PMIC chip, the DLPC150 takes much longer than 40 µs to park the mirrors. The DLPA200x holds on all power supplies, and keep RESETZ high, until the longer mirror parking has completed. This longer mirror parking time, of up to 20 ms, ensures the longest DMD lifetime and reliability. The DLPA2000 or DLPA2005 monitors power to the DLPC150 and detects an eminent power loss condition and drives the PARKZ signal accordingly. Connect to the interrupt output pin of the DLPA2000 or DLPA2005 PMIC.
PROJ_ON	G14	B₁	Normal mirror parking request (active low): To be driven by the PROJ_ON output of the host. A logic low on this signal will cause the DLPC150 to PARK the DMD, but it will not power down the DMD (the DLPA2000 or DLPA2005 controls the power down). The minimum high time is 200 ms. The minimum low time is also 200 ms.
HOST_IRQ⁽²⁾	N8	O₉	Host interrupt (output) This signal has two primary uses. The first use is to indicate when DLPC150 auto-initialization is in progress and most importantly when it completes. The second is to indicate when service is requested (that is an interrupt request). The DLPC150 tri-states this output during reset and requires an external pullup to drive this signal to its inactive state.
IIC0_SCL	N10	B₇	I²C slave (port 0) SCL A bidirectional, open-drain signal with input hysteresis that requires an external pullup. The slave I²C I/Os are 3.6-V tolerant (high-volt-input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I²C pullups must be connected to an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage would not likely satisfy the VIH specification of the slave I²C input buffers).
IIC0_SDA	N9	B₇	I²C slave (port 0) SDA. A bidirectional, open-drain signal with input hysteresis that requires an external pullup. The slave I²C I/Os are 3.6-V tolerant (high-volt-input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I²C pullups must be connected to an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage would not likely satisfy the VIH specification of the slave I²C input buffers).
PARALLEL PORT INPUT DATA AND CONTROL
PCLK	P3	I₁₁	Pixel clock⁽⁵⁾
PDM_CVS_TE	N4	B₅	Parallel data mask⁽³⁾
VSYNC_WE	P1	I₁₁	Vsync⁽⁴⁾
HSYNC_CS	N5	I₁₁	Hsync⁽⁴⁾
DATAEN_CMD	P2	I₁₁	Data valid active high framing signal.⁽⁴⁾ DLPC150 also offers a manual data framing mode through a software command. Refer to the DLPC150 Programmer's Guide for more information on the manual data framing command.
			(TYPICAL RGB 888)
PDATA_0 PDATA_1 PDATA_2 PDATA_3 PDATA_4 PDATA_5 PDATA_6 PDATA_7	K2 K1 L2 L1 M2 M1 N2 N1	I₁₁	Blue Blue Blue Blue Blue Blue Blue Blue
			(TYPICAL RGB 888)
PDATA_8 PDATA_9 PDATA_10 PDATA_11 PDATA_12 PDATA_13 PDATA_14 PDATA_15	R1 R2 R3 P4 R4 P5 R5 P6	I₁₁	Green Green Green Green Green Green Green Green
			(TYPICAL RGB 888)
PDATA_16 PDATA_17 PDATA_18 PDATA_19 PDATA_20 PDATA_21 PDATA_22 PDATA_23	R6 P7 R7 P8 R8 P9 R9 P10	I₁₁	Red Red Red Red Red Red Red Red
DMD RESET AND BIAS CONTROL
DMD_DEN_ARSTZ	B1	O₂	DMD driver enable (active high)/ DMD reset (active low). Assuming the corresponding I/O power is supplied, this signal will be driven low after the DMD is parked and before power is removed from the DMD. If the 1.8-V power to the DLPC150 is independent of the 1.8-V power to the DMD, then TI recommends a weak, external pulldown resistor to hold the signal low in the event DLPC150 power is inactive while DMD power is applied.
DMD_LS_CLK	A1	O₃	DMD, low speed interface clock
DMD_LS_WDATA	A2	O₃	DMD, low speed serial write data
DMD_LS_RDATA	B2	I₆	DMD, low speed serial read data
DMD SUB-LVDS INTERFACE
DMD_HS_CLK_P DMD_HS_CLK_N	A7 B7	O₄	DMD high speed interface
DMD_HS_WDATA_H_P DMD_HS_WDATA_H_N DMD_HS_WDATA_G_P DMD_HS_WDATA_G_N DMD_HS_WDATA_F_P DMD_HS_WDATA_F_N DMD_HS_WDATA_E_P DMD_HS_WDATA_E_N DMD_HS_WDATA_D_P DMD_HS_WDATA_D_N DMD_HS_WDATA_C_P DMD_HS_WDATA_C_N DMD_HS_WDATA_B_P DMD_HS_WDATA_B_N DMD_HS_WDATA_A_P DMD_HS_WDATA_A_N	A3 B3 A4 B4 A5 B5 A6 B6 A8 B8 A9 B9 A10 B10 A11 B11	O₄	DMD high speed interface lanes, write data bits: (The true numbering and application of the DMD_HS_DATA pins are software configuration dependent)
SERIAL FLASH MEMORY INTERFACE
SPI0_CLK	A13	O₁₃	Synchronous serial port 0, clock output. Connect to clock input pin of the serial Flash memory device.
SPI0_CSZ0	A14	O₁₃	Synchronous serial port 0, chip select 0 output. Active low output. Connect to chip select pin of the serial Flash memory device. TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during DLPC150 controller reset assertion.
SPI0_CSZ1	C12	O₁₃	Synchronous serial port 0, chip select 1 output. Active low output. Connect to chip select pin of a second serial Flash memory device. TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during DLPC150 controller reset assertion.
SPI0_DIN	B12	I₁₂	Synchronous serial port 0, receive data input. Connect to the data output of the serial Flash memory device.
SPI0_DOUT	B13	O₁₃	Synchronous serial port 0, transmit data output. Connect to the data input of the serial Flash memory device.
DLPA2000 OR DLPA2005 PMIC INTERFACE
PMIC_SPI_CLK	C15	B₁	Synchronous PMIC serial port, clock output. Connect to the clock input (SPI_CLK) of the DLPA2000 or DLPA2005 PMIC.
PMIC_SPI_CSZ	D15	B₁	Synchronous PMIC serial port, chip select output. Active low output. Connect to the chip select input (SPI_CSZ) of the DLPA2000 or DLPA2005 PMIC. TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during DLPC150 controller reset assertion.
PMIC_SPI_DIN	C14	B₁	Synchronous PMIC serial port, receive data input. Connect to the data output (SPI_DOUT) of the DLPA2000 or DLPA2005 PMIC.
PMIC_SPI_DOUT	D14	B₁	Synchronous PMIC serial port, receive data output. Connect to the data input (SPI_DIN) of the DLPA2000 or DLPA2005 PMIC.
PMIC_CMP_IN	A12	I₆	Successive approximation ADC comparator input. Assumes a successive approximation ADC is implemented with a WPC light sensor and/or a thermistor feeding one input of an external comparator and the other side of the comparator is driven from the DLPC150 controller’s CMP_PWM pin. Connect to the analog comparator output (CMP_OUT) of the DLPA2000 or DLPA2005 PMIC. If this function is not used, pulled-down to ground.
PMIC_CMP_PWM	A15	O₁	Successive approximation comparator pulse-duration modulation output. Supplies a PWM signal to drive the successive approximation ADC comparator used in WPC light-to-voltage sensor applications. Connect to the reference voltage input for analog comparator (PWM_IN) of the DLPA2000 or DLPA2005. If this function is not used, leave this pin unconnected.
PMIC_LED_SEL_0	B15	O₁	LED enable select. Controlled by programmable DMD sequence
LED_SEL(1:0)			Enabled LED Timing DLPA2000 or DLPA2005 application 00 = None 01 = Red 10 = Green 11 = Blue
PMIC_LED_SEL_1	B14	O₁	These signals will be driven low when RESETZ is asserted and the corresponding I/O power is supplied. They will continue to be driven low throughout the auto-initialization process. A weak, external pulldown resistor is still recommended to ensure that the LEDs are disabled when I/O power is not applied.
TRIGGER CONTROL
TRIG_IN_1	N6	I₁₁	Input Trigger mode 1. Active high input signal that display the next pattern in the pattern sequence. Pull-down this signal with an external resistor.
TRIG_OUT_1	L14	B₁	Output Trigger mode 1. Active high output signal during pattern exposure
TRIG_OUT_2	E14	B₁	Output Trigger mode 2. Active high output signal that indicates the first pattern in a sequence.
GPIO PERIPHERAL INTERFACE
GPIO_19	M15	B₁	General purpose I/O 19 (hysteresis buffer). Options: Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input). KEYPAD_4 (input): keypad applications
GPIO_18	M14	B₁	General purpose I/O 18 (hysteresis buffer). Options: Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input). KEYPAD_3 (input): keypad applications
GPIO_17	L15	B₁	General purpose I/O 17 (hysteresis buffer). Options: Optional GPIO. Configured as a logic zero GPIO output and left unconnected if not used.
GPIO_15	K15	B₁	General purpose I/O 15 (hysteresis buffer). Options: Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input). KEYPAD_0 (input): keypad applications
GPIO_14	K14	B₁	General purpose I/O 14 (hysteresis buffer). Option: Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).
GPIO_13	J15	B₁	General purpose I/O 13 (hysteresis buffer). Options: CAL_PWR (output): Intended to feed the calibration control of the successive approximation ADC light sensor. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).
GPIO_12	J14	B₁	General purpose I/O 12 (hysteresis buffer). Option: Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).
GPIO_11	H15	B₁	General purpose I/O 11 (hysteresis buffer). Options: (Output): thermistor power enable. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).
GPIO_10	H14	B₁	General Purpose I/O 10 (hysteresis buffer). Options: RC_CHARGE (output): Intended to feed the RC charge circuit of the successive approximation ADC used to control the light sensor comparator. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).
GPIO_09	G15	B₁	General purpose I/O 09 (hysteresis buffer). Options: LS_PWR (active high output): Intended to feed the power control signal of the successive approximation ADC light sensor. Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).
GPIO_07	F15	B₁	General purpose I/O 07 (hysteresis buffer). Options: (All) LED_ENABLE (active high input). This signal can be used as an optional shutdown interlock for the LED driver. Specifically, when so configured, setting LED_ENABLE = 0 (disabled), will cause LDEDRV_ON to be forced to 0 and LED_SEL(2:0) to be forced to b000. Otherwise when LED_ENABLE = 1 (enabled), the DLPC150 controller is free to control the LED SEL signals as it desires. There is however a 100-ms delay after LED_ENABLE transitions from low-to-high before the interlock is released. (Output): LABB output sample and hold sensor control signal. (All) GPIO (bidirectional): Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).
GPIO_06	F14	B₁	General purpose I/O 06 (hysteresis buffer). Option: Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used. An external pulldown resistor is required to deactivate this signal during reset and auto-initialization processes.
GPIO_05	E15	B₁	General purpose I/O 05 (hysteresis buffer). Option: Optional GPIO. Should be configured as a logic zero GPIO output and left unconnected if not used (otherwise it will require an external pullup or pulldown to avoid a floating GPIO input).
CLOCK AND PLL SUPPORT
PLL_REFCLK_I	H1	I₁₁	Reference clock crystal input. If an external oscillator is used in place of a crystal, then this pin serves as the oscillator input.
PLL_REFCLK_O	J1	O₅	Reference clock crystal return. If an external oscillator is used in place of a crystal, then leave this pin unconnected with no capacitive load.
BOARD LEVEL TEST AND DEBUG
HWTEST_EN	C10	I₆	Reserved Manufacturing test enable pin. For proper device operation, connect this signal directly to ground.
Reserved	P12	I₆	Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	P13	I₆	Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	N13⁽⁶⁾	O₁	Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	N12⁽⁶⁾	O₁	Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	R10	B₈	Reserved pin. For proper device operation, pull high to V_cc18 with external pullup resistor.
Reserved	R11	B₈	Reserved pin. For proper device operation, pull high to V_cc18 with external pullup resistor.
Reserved	M13	I₆	Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	N11	I₆	Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	P11	I₆	Reserved pin. For proper device operation, this pin must be tied to ground, through an external 8-kΩ, or less, resistor. Failure to tie this pin low will cause startup and initialization problems.
Reserved	E1		Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	E2		Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	F1		Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	F2		Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	F3		Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	G1		Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	G2		Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	D1		Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	D2		Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	C1		Reserved pin. For proper device operation, leave this pin unconnected.
Reserved	C2		Reserved pin. For proper device operation, leave this pin unconnected.
TSTPT_0	R12	B₁	Reserved Test pin 0. For proper device operation, leave this pin unconnected (includes weak internal pulldown).Tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ, and then driven as an output. Note: An external pullup should not be applied to this pin to avoid putting the DLPC150 in a test mode.
TSTPT_1	R13	B₁	Reserved Test pin 1. For proper device operation, leave this pin unconnected (includes weak internal pulldown). Tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output. Note: An external pullup should not be applied to this pin to avoid putting the DLPC150 in a test mode.
TSTPT_2	R14	B₁	Reserved Test pin 2. For proper device operation, leave this pin unconnected (includes weak internal pulldown). Tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output. Note: An external pullup should not be applied to this pin to avoid putting the DLPC150 in a test mode.
TSTPT_3	R15	B₁	Reserved Test pin 3. For proper device operation, leave this pin unconnected (includes weak internal pulldown).Tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
TSTPT_4	P14	B₁	Reserved Test pin 4. For proper device operation, leave this pin unconnected (includes weak internal pulldown).Tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
TSTPT_5	P15	B₁	Reserved Test pin 5. For proper device operation, leave this pin unconnected (includes weak internal pulldown). Tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
TSTPT_6	N14	B₁	Reserved Test pin 6. For proper device operation, leave this pin unconnected (includes weak internal pulldown). Tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
TSTPT_7	N15	B₁	Reserved Test pin 7. For proper device operation, leave this pin unconnected (includes weak internal pulldown). Tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ and then driven as an output.
POWER AND GROUND
VDD	C5, D5, D7, D12, J4, J12, K3, L4, L12, M6, M9, D9, D13, F13, H13, L13, M10, D3, E3	PWR	Core power 1.1 V (main 1.1 V)
VDDLP12	C3	PWR	Core power 1.1 V
VSS	C4, D6, D8, D10, E4, E13, F4, G4, G12, H4, H12, J3, J13, K4, K12, L3, M4, M5, M8, M12, G13, C6, C8, F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9, K10	GND	Core ground (eDRAM, I/O ground, thermal ground)
VCC18	C7, C9, D4, E12, F12, K13, M11	PWR	All 1.8-V I/O power: (1.8-V power supply for all I/O other than the host or parallel interface and the SPI flash interface. This includes RESETZ, PARKZ LED_SEL, CMP, GPIO, IIC1, TSTPT, and JTAG pins)
VCC_INTF	M3, M7, N3, N7	PWR	Host or parallel interface I/O power: 1.8 to 3.3 V (Includes IIC0, PDATA, video syncs, and HOST_IRQ pins)
VCC_FLSH	D11	PWR	Flash interface I/O power:1.8 to 3.3 V (Dedicated SPI0 power pin)
VDD_PLLM	H2	PWR	MCG PLL 1.1-V power
VSS_PLLM	G3	RTN	MCG PLL return
VDD_PLLD	J2	PWR	DCG PLL 1.1-V power
VSS_PLLD	H3	RTN	DCG PLL return

(1) Refer to Table 1.

(2) For more information about usage, see Host_irq Usage Model.

(3) The parallel data mask signal input is optional for parallel interface operations. If unused, inputs should be grounded or pulled down to ground through an external resistor (8 kΩ or less).

(4) VSYNC, HSYNC, and DATAEN polarity is software programmable.

(5) Pixel clock capture edge is software programmable.

(6) If operation does not call for an external pullup and there is no external logic that might overcome the weak internal pulldown resistor, then this I/O can be left open or unconnected for normal operation. If operation does not call for an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a logic low.