ZHCSIF8I December   2015  – August 2024 DLPC230-Q1 , DLPC231-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Electrical Characteristics for Fixed Voltage I/O
    7. 5.7  DMD High-Speed SubLVDS Electrical Characteristics
    8. 5.8  DMD Low-Speed SubLVDS Electrical Characteristics
    9. 5.9  OpenLDI LVDS Electrical Characteristics
    10. 5.10 Power Dissipation Characterisics
    11. 5.11 System Oscillators Timing Requirements
    12. 5.12 Power Supply and Reset Timing Requirements
    13. 5.13 Parallel Interface General Timing Requirements
    14. 5.14 OpenLDI Interface General Timing Requirements
    15. 5.15 Parallel/OpenLDI Interface Frame Timing Requirements
    16. 5.16 Host/Diagnostic Port SPI Interface Timing Requirements
    17. 5.17 Host/Diagnostic Port I2C Interface Timing Requirements
    18. 5.18 Flash Interface Timing Requirements
    19. 5.19 TPS99000-Q1 SPI Interface Timing Requirements
    20. 5.20 TPS99000-Q1 AD3 Interface Timing Requirements
    21. 5.21 DLPC23x-Q1 I2C Port Interface Timing Requirements
    22. 5.22 Chipset Component Usage Specification
  7. 6 Parameter Measurement Information
    1. 6.1 HOST_IRQ Usage Model
    2. 6.2 Input Source
      1. 6.2.1 Supported Input Sources
      2. 6.2.2 Parallel Interface Supported Data Transfer Formats
        1. 6.2.2.1 OpenLDI Interface Supported Data Transfer Formats
          1. 6.2.2.1.1 OpenLDI Interface Bit Mapping Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Parallel Interface
      2. 7.3.2  OpenLDI Interface
      3. 7.3.3  DMD (SubLVDS) Interface
      4. 7.3.4  Serial Flash Interface
      5. 7.3.5  Serial Flash Programming
      6. 7.3.6  Host Command and Diagnostic Processor Interfaces
      7. 7.3.7  GPIO Supported Functionality
      8. 7.3.8  Built-In Self Test (BIST)
      9. 7.3.9  EEPROMs
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Debug Support
    4. 7.4 Device Functional Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Display Mode
      3. 7.4.3 Calibration Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Head-Up Display
        1. 8.2.1.1 Design Requirements
      2. 8.2.2 Headlight
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Headlight Video Input
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Management
      2. 8.3.2 Hot Plug Usage
      3. 8.3.3 Power Supply Filtering
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1  PCB Layout Guidelines for Internal ASIC PLL Power
        2. 8.4.1.2  DLPC23x-Q1 Reference Clock
          1. 8.4.1.2.1 Recommended Crystal Oscillator Configuration
        3. 8.4.1.3  DMD Interface Layout Considerations
        4. 8.4.1.4  General PCB Recommendations
        5. 8.4.1.5  General Handling Guidelines for Unused CMOS-Type Pins
        6. 8.4.1.6  Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
        7. 8.4.1.7  Number of Layer Changes
        8. 8.4.1.8  Stubs
        9. 8.4.1.9  Terminations
        10. 8.4.1.10 Routing Vias
        11. 8.4.1.11 Layout Examples
      2. 8.4.2 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 9.1.2 Device Nomenclature
        1. 9.1.2.1 Device Markings DLPC230-Q1 or DLPC230S-Q1
        2. 9.1.2.2 Device Markings DLPC231-Q1 or DLPC231S-Q1
        3. 9.1.2.3 Video Timing Parameter Definitions
    2. 9.2 Trademarks
    3. 9.3 静电放电警告
    4. 9.4 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.3.3 DMD (SubLVDS) Interface

The DLPC23x-Q1 ASIC DMD interface supports two high-speed SubLVDS output-only interfaces for data transmission, a single low-speed SubLVDS output-only interface for command write transactions, as well as a low-speed single-ended input interface used for command read transactions. The DLPC23x-Q1 supports a limited number of DMD interface swap configurations (specified in Flash) that can help board layout by remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 7-1 shows some of the options available.

Table 7-1 ASIC to 8-Lane DMD Pin Mapping Options
DLPC23x-Q1 ASIC PIN ROUTING OPTIONS TO DMD PINSDMD PINS
BASELINEFULL FLIP HS0/HS1 180SWAP HS0 PORT WITH HS1 PORTSWAP HS0 PORT WITH HS1 PORT AND FULL FLIP 180
HS0_WDATA0_P
HS0_WDATA0_N		HS0_WDATA7_P
HS0_WDATA7_N		HS1_WDATA0_P
HS1_WDATA0_N		HS1_WDATA7_P
HS1_WDATA7_N		D_AP(0)
D_AN(0)
HS0_WDATA1_P
HS0_WDATA1_N		HS0_WDATA6_P
HS0_WDATA6_N		HS1_WDATA1_P
HS1_WDATA1_N		HS1_WDATA6_P
HS1_WDATA6_N		D_AP(1)
D_AN(1)
HS0_WDATA2_P
HS0_WDATA2_N		HS0_WDATA5_P
HS0_WDATA5_N		HS1_WDATA2_P
HS1_WDATA2_N		HS1_WDATA5_P
HS1_WDATA5_N		D_AP(2)
D_AN(2)
HS0_WDATA3_P
HS0_WDATA3_N		HS0_WDATA4_P
HS0_WDATA4_N		HS1_WDATA3_P
HS1_WDATA3_N		HS1_WDATA4_P
HS1_WDATA4_N		D_AP(3)
D_AN(3)
HS0_WDATA4_P
HS0_WDATA4_N		HS0_WDATA3_P
HS0_WDATA3_N		HS1_WDATA4_P
HS1_WDATA4_N		HS1_WDATA3_P
HS1_WDATA3_N		D_AP(4)
D_AN(4)
HS0_WDATA5_P
HS0_WDATA5_N		HS0_WDATA2_P
HS0_WDATA2_N		HS1_WDATA5_P
HS1_WDATA5_N		HS1_WDATA2_P
HS1_WDATA2_N		D_AP(5)
D_AN(5)
HS0_WDATA6_P
HS0_WDATA6_N		HS0_WDATA1_P
HS0_WDATA1_N		HS1_WDATA6_P
HS1_WDATA6_N		HS1_WDATA1_P
HS1_WDATA1_N		D_AP(6)
D_AN(6)
HS0_WDATA7_P
HS0_WDATA7_N		HS0_WDATA0_P
HS0_WDATA0_N		HS1_WDATA7_P
HS1_WDATA7_N		HS1_WDATA0_P
HS1_WDATA0_N		D_AP(7)
D_AN(7)
HS1_WDATA0_P
HS1_WDATA0_N		HS1_WDATA7_P
HS1_WDATA7_N		HS0_WDATA0_P
HS0_WDATA0_N		HS0_WDATA7_P
HS0_WDATA7_N		D_BP(0)
D_BN(0)
HS1_WDATA1_P
HS1_WDATA1_N		HS1_WDATA6_P
HS1_WDATA6_N		HS0_WDATA1_P
HS0_WDATA1_N		HS0_WDATA6_P
HS0_WDATA6_N		D_BP(1)
D_BN(1)
HS1_WDATA2_P
HS1_WDATA2_N		HS1_WDATA5_P
HS1_WDATA5_N		HS0_WDATA2_P
HS0_WDATA2_N		HS0_WDATA5_P
HS0_WDATA5_N		D_BP(2)
D_BN(2)
HS1_WDATA3_P
HS1_WDATA3_N		HS1_WDATA4_P
HS1_WDATA4_N		HS0_WDATA3_P
HS0_WDATA3_N		HS0_WDATA4_P
HS0_WDATA4_N		D_BP(3)
D_BN(3)
HS1_WDATA4_P
HS1_WDATA4_N		HS1_WDATA3_P
HS1_WDATA3_N		HS0_WDATA4_P
HS0_WDATA4_N		HS0_WDATA3_P
HS0_WDATA3_N		D_BP(4)
D_BN(4)
HS1_WDATA5_P
HS1_WDATA5_N		HS1_WDATA2_P
HS1_WDATA2_N		HS0_WDATA5_P
HS0_WDATA5_N		HS0_WDATA2_P
HS0_WDATA2_N		D_BP(5)
D_BN(5)
HS1_WDATA6_P
HS1_WDATA6_N		HS1_WDATA1_P
HS1_WDATA1_N		HS0_WDATA6_P
HS0_WDATA6_N		HS0_WDATA1_P
HS0_WDATA1_N		D_BP(6)
D_BN(6)
HS1_WDATA7_P
HS1_WDATA7_N		HS1_WDATA0_P
HS1_WDATA0_N		HS0_WDATA7_P
HS0_WDATA7_N		HS0_WDATA0_P
HS0_WDATA0_N		D_BP(7)
D_BN(7)
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