ZHCSLG8E August 2020 – August 2024 DLPC230S-Q1 , DLPC231S-Q1
PRODUCTION DATA
The DLPC23xS-Q1 uses an external SPI serial flash memory device for configuration and operational data. The minimum supported size is 16 Mb. Larger devices can be required based on operation data and splash image size. The maximum supported size is 128 Mb. It must be noted that the system will support 256 Mb and 512 Mb devices, however, only the first 128 Mb of space are used.
The external serial flash device is supported on a single SPI interface and mostly complies with industry standard SPI flash protocol (See Figure 5-8). The Host will specify the maximum supported flash interface frequency (which can be based on device limits, system limits, and/or other factors) and the system will program the closest obtainable value less than or equal to this specified maximum.
The DLPC23xS-Q1 ASIC flash must be connected to the designated SPI flash interface (FLSH_SPI_xxx) to enable support for system initialization, configuration, and operation.
The DLPC23xS-Q1 must support any flash device that is compatible with the modes of operation, features, and performance as defined in this section.
| FEATURE | DLPC23xS-Q1 REQUIREMENT | COMMENTS |
|---|---|---|
| SPI interface width | Single Wire, Two Wire, Four Wire | |
| SPI protocol | SPI mode 0 | |
| Fast READ addressing | Auto-incrementing | |
| Programming mode | Page mode | |
| Page size | 256 Bytes | |
| Sector (or Subsector) size | 4 KB | Required erase granularity |
| Block structure | Uniform sector / Subsector | |
| Block protection bits | 0 = Disabled (with Default = 0 = Disabled) | |
| Status register bit(0) | Write in progress (WIP) {also called flash busy} | |
| Status register bit(1) | Write enable latch (WEN) | |
| Status register bits(6:2) | A value of 0 disables programming protection | |
| Status register bit(7) | Status register write protect (SRWP) | |
| Status register bits(15:8) (expanded status register), or Secondary Status register | The DLPC23xS-Q1 supports multi-byte status registers, as well as separate, additional status registers, but only for specific devices/register addresses. The supported registers and addresses are specified in Table 7-3. |
The selected SPI flash device must block repeated status writes from being written to internal register. The boot application writes to the flash device status register once per 256 bytes during programming. Most flash devices discard status register writes when the status content does not change. Some flash parts, such as the Micron N25Q128A13ESFA0F, do not block status writes when the status data is repeated. This causes the status register to exceed its maximum write limit after several programming cycles, making them incompatible with the DLPC23xS-Q1. Note that the main application does not write to the status register.
For each write operation, the DLPC23xS-Q1 boot application executes the following:
For each write operation, the DLPC23xS-Q1 main application executes the following:
The specific instruction op-code and timing compatibility requirements are listed in Table 7-3 and Flash Interface Timing Requirements. Note that DLPC23xS-Q1 does not read the flash’s full electronic signature ID and thus cannot automatically adapt protocol and clock rates based on the ID.
| SPI FLASH COMMAND | FIRST BYTE (OP-CODE) | SECOND BYTE | THIRD BYTE | FOURTH BYTE | FIFTH BYTE | SIXTH BYTE | NO. OF DUMMY CLOCKS | COMMENTS |
|---|---|---|---|---|---|---|---|---|
| Fast READ (1/1) | 0x0B | ADDRS(0) | ADDRS(1) | ADDRS(2) | dummy | DATA(0)(1) | 8 | See Table 7-4. |
| Dual READ (1/2) | 0x3B | ADDRS(0) | ADDRS(1) | ADDRS(2) | dummy | DATA(0)(1) | 8 | See Table 7-4. |
| 2X READ (2/2) | 0xBB | ADDRS(0) | ADDRS(1) | ADDRS(2) | dummy | DATA(0)(1) | 4 | See Table 7-4. |
| Quad READ (1/4) | 0x6B | ADDRS(0) | ADDRS(1) | ADDRS(2) | dummy | DATA(0)(1) | 8 | See Table 7-4. |
| 4X READ (4/4) | 0xEB | ADDRS(0) | ADDRS(1) | ADDRS(2) | dummy | DATA(0)(1) | 6 | See Table 7-4. |
| Read status | 0x05 | n/a | n/a | STATUS(0) | STATUS(1) | 0 | Status(1) - Winbond only | |
| Write status | 0x01 | STATUS(0) | STATUS(1) | 0 | Status(1) - Winbond only | |||
| Read Volatile Conf Reg | 0x85 | Data(0) | 0 | Micron Only | ||||
| Write Volatile Conf Reg | 0x81 | Data(0) | 0 | Micron Only | ||||
| Write Enable | 0x06 | 0 | ||||||
| Write Disable | 0x04 | 0 | ||||||
| Page program | 0x02 | ADDRS(0) | ADDRS(1) | ADDRS(2) | DATA(0)(1) | 0 | ||
| Sector/Subsector Erase (4KB) | 0x20 | ADDRS(0) | ADDRS(1) | ADDRS(2) | 0 | |||
| Full Chip Erase | 0xC7 | 0 | ||||||
| Software Reset Enable | 0x66 | |||||||
| Software Reset | 0x99 | |||||||
| Read Id | 0x9F | Data(0) | Data(1) | Data(2) | System only reads 1st three bytes. |
More detailed information on the various read operations supported are shown in Table 7-4.
| READ TYPE(2) | NUMBER OF LINES FOR OP-CODE(1) | NUMBER OF LINES FOR ADDRESS | NUMBER OF LINES FOR DUMMY BYTES | NUMBER OF LINES FOR RETURN DATA |
|---|---|---|---|---|
| Fast Read (1/1) | 1 | 1 | 1 | 1 |
| Dual Read (1/2) | 1 | 1 | 1 | 2 |
| 2X Read (2/2) | 1 | 2 | 2 | 2 |
| Quad Read (1/4) | 1 | 1 | 1 | 4 |
| 4X Read (4/4) | 1 | 4 | 4 | 4 |
| DENSITY (M-BITS) (2)(3) | VENDOR | PART NUMBER | PACKAGE SIZE |
|---|---|---|---|
| 3.3V Compatible Devices | |||
| 128 | Micron(1) | MT25QL128ABA8ESF-OAAT | SO16 |
| 128 | Macronix | MX25L12835FMR-10G | SO16 |
| 128 | Macronix | MX25L12845GMR-10G | SO16 |
| 128 | Macronix | MX25L12839FXDQ-10G | BGA25 |
While the DLPC23xS-Q1 supports a variety of clock rates and read operation types, it does have a minimum flash read bandwidth requirement which is shown in Table 7-6. This minimum read bandwidth can be met in any number of different ways, with the variables being clock rate and read type. The Host is required to select a flash device which can meet this minimum read bandwidth using the DLPC23xS-Q1 supported interface capabilities. It must be noted that the Host will specify to the system (through flash parameter) the maximum supported clock rate as well as the supported read types for their selected flash device, with which the DLPC23xS-Q1 SW will automatically select an appropriate combination to maximize this bandwidth (which must at least meet the minimum bandwidth requirement assuming a solution exists per the specified parameters).
| PARAMETER | MIN | MAX | UNIT | |
|---|---|---|---|---|
| FLSH_RDBW | Flash Read Interface Bandwidth | 47.00 | Mbps | |