The following guidelines are recommended to achieve the desired ASIC performance relative to the internal PLL. The DLPC23xS-Q1 contains two internal PLLs that have dedicated analog supplies (VCC11AD_PLLM, GND11AD_PLLM, VCC11AD_PLLD, GND11AD_PLLD). At a minimum, VCC11AD_PLLx power and GND11AD_PLLx ground pins must be isolated using a simple passive filter consisting of two series ferrites and two shunt capacitors (to widen the spectrum of noise absorption). Recommended values and layout are shown in Table 8-1 and Figure 8-10, respectively.

Because the PCB layout is critical to PLL performance, it is vital that the quiet ground and power are treated like analog signals. Additional design guidelines are as follows:

• All four components must be placed as close to the ASIC as possible.
• It is especially important to keep the leads of the high-frequency capacitors as short as possible.
• A capacitor of each value must be connected across VCC11AD_PLLM / GND11AD_PLLM and VCC11AD_PLLD / GND11AD_PLLD respectively on the ASIC side of the ferrites.
• VCC11AD_PLLM and VCC11AD_PLLD must be a single trace from the DLPC23xS-Q1 to both capacitors and then through the series of ferrites to the power source.
• The power and ground traces must be as short as possible, parallel to each other, and as close as possible to each other.

Figure 8-10 DLPC230S-Q1 PLL Filter Layout

Figure 8-11 DLPC231S-Q1 PLL Filter and Crystal Layout