The DLPC23xS-Q1 contains a test point output port, TSTPT_(7:0), which provides the Host with the ability to specify a number of initial system configurations, as well as to provide for ASIC debug support. These test points are tristated while reset is applied, are sampled as inputs approximately 1.5µs after reset is released, and then switch to outputs after the input values have been sampled. The sampled and captured input state for each of these signals is used to configure initial system configurations as specified in the table Pin Functions—Parallel Port Input Data and Control in Section 4.

There are three other signals (JTAGTDO(3:1)) that are sampled as inputs approximately 1.5µs after reset is released, and then switched to outputs. The sampled and captured state for each of these JTAGTDO signals is used to configure the initial test mode output state of the TSTPT_(7:0) signals. Table 7-10 defines the test mode selection for a few programmable output states for TSTPT_(7:0) as defined by JTAGTDO(3:1). For normal use (that is, no debug required), the default state of x111 (using weak internal pullups) must be used to allow for the normal use of these JTAG TDO signals.

To allow TI to make use of this debug capability, a jumper to an external pulldown is recommended for JTAGTDO(3:1).