米6体育平台手机版

ZHCSC07E December 2013 – March 2019 DLPC2607

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

ZVB|176

散热焊盘机械数据 (封装 | 引脚)

6.8 Parallel I/F Frame Timing Requirements

			MIN	MAX	UNIT
t_{p_vsw}	Pulse duration – VSYNC_WE high	50% reference points	1		lines
t_{p_vbp}	Vertical back porch – Time from the leading edge of VSYNC_WE to the leading edge HSYNC_CS for the first active line.⁽²⁾	50% reference points	2		lines
t_{p_vfp}	Vertical front porch – Time from the leading edge of the HSYNC_CS following the last active line in a frame to the leading edge of VSYNC_WE.⁽²⁾	50% reference points	1		lines
t_{p_tvb}	Total vertical blanking – Time from the leading edge of HSYNC_CS following the last active line of one frame to the leading edge of HSYNC_CS for the first active line in the next frame. This is equal to the sum of Vertical back porch (t_{p_vbp}) + Vertical front porch (t_{p_vfp}).	50% reference points	12		lines
t_{p_hsw}	Pulse duration – HSYNC_CS high	50% reference points	4	128	PCLKs
t_{p_hbp}	Horizontal back porch – Time from rising edge of HSYNC_CS to rising edge of DATAEN_CMD.	50% reference points	4		PCLKs
t_{p_hfp}	Horizontal front porch – Time from falling edge of DATAEN_CMD to rising edge of HSYNC_CS.	50% reference points	8		PCLKs
t_{p_thh}	Total horizontal blanking – Sum of horizontal front and back porches	50% reference points	⁽¹⁾		PCLKs

(1) Total horizontal blanking is driven by the max line rate for a given source, which is a function of resolution and orientation. See Parallel I/F Maximum Parallel Interface Horizontal Line Rate for max line rate for each source and display combination. t_{p_thb} = Roundup [(1000 x ƒ_clock)/ LR] – APPL where ƒ_clock = Pixel clock rate in MHz, LR = Line rate in kHz, and the number of active pixels per (horizontal) line is APPL. If t_{p_thb} is calculated to be less than t_{p_hbp} + t_{p_hfp}, then the pixel clock rate is too low, or the line rate is too high, and one or both must be adjusted.

(2) The programmable parameter vertical sync line delay (I²C: 0x23) must be set such that:
6 – Vertical front porch (t_{p_vfp})’ (min 0) ≤ Vertical sync line delay ≤ Vertical back porch (tp_{_vbp}) – 2 (max 15). The default value for vertical sync line delay is set to 5; thus, only a vertical back porch less than 7 requires potential action.