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ZHCSC07E December 2013 – March 2019 DLPC2607

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

ZVB|176

散热焊盘机械数据 (封装 | 引脚)

6.13 Flash Interface Timing Requirements

The DLPC2607 ASIC flash memory interface consists of a SPI flash serial interface at 33.3 MHz (nominal). ⁽²⁾⁽³⁾

			MIN	MAX	UNIT
ƒ_clock	Clock frequency, SPI_CLK⁽¹⁾		33.3266	33.34	MHz
t_{p_clkper}	Clock period, SPI_CLK	50% reference points	29.994	30.006	ns
t_{p_wh}	Pulse duration low, SPI_CLK	50% reference points	10		ns
t_{p_wl}	Pulse duration high, SPI_CLK	50% reference points	10		ns
t_t	Transition time – all signals	20% to 80% reference points	0.2	4	ns
t_{p_su}	Setup time – SPI_DIN valid before SPI_CLK falling edge	50% reference points	10		ns
t_{p_h}	Hold time – SPI_DIN valid after SPI_CLK falling edge	50% reference points	0		ns
t_{p_clqv}	SP_ICLK clock low to output valid time – SPIDOUT and SPI_CSZ	50% reference points		1	ns
t_{p_clqx}	SPI_CLK clock low output hold time – SPI_DOUT and SPI_CSZ	50% reference points	–1		ns

(1) This range includes the 200 ppm of the external oscillator (but no jitter).

(2) Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC2607 device does transmit data on the falling edge, but it captures data on the falling edge rather than the rising edge. This provides support for SPI devices with long clock-to-Q timing. The DLPC2607 device hold capture timing is set to facilitate reliable operation with standard external SPI protocol devices.

(3) With the above output timing, the DLPC2607 device provides the external SPI device 14-ns input set-up and 14-ns input hold relative to the rising edge of SPI_CLK.