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ZHCSC07E December 2013 – March 2019 DLPC2607

PRODUCTION DATA.

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

ZVB|176

散热焊盘机械数据 (封装 | 引脚)

6.14 DMD Interface Timing Requirements

The DLPC2607 ASIC DMD interface consists of a 76.19-MHz (nominal) DDR output-only interface with LVCMOS signaling. (see ⁽⁵⁾)

			MIN	MAX	UNIT
ƒ_clock	Clock frequency, DMD_DCLK and DMD_SAC_CLK⁽¹⁾		76.175	76.206	MHz
t_{p_clkper}	Clock period, DMD_DCLK and DMD_SAC_CLK	50% reference points	13.122	13.128	ns
t_{p_wh}	Pulse duration low, DMD_DCLK and DMD_SAC_CLK	50% reference points	6.2		ns
t_{p_wl}	Pulse duration high, DMD_DCLK and DMD_SAC_CLK	50% reference points	6.2		ns
t_t	Transition time – all signals	20% to 80% reference points	0.3	2	ns
t_{p_su}	Output setup time – DMD_D(14:0), DMD_SCTRL, DMD_LOADB and DMD_TRC relative to both rising and falling edges of DMD_DCLK⁽²⁾⁽⁴⁾	50% reference points		1.5	ns
t_{p_h}	Output hold time – DMD_D(14:0), DMD_SCTRL,DMD_LOADB and DMD_TRC signals relative to both rising and falling edges of DMD_DCLK⁽²⁾⁽⁴⁾	50% reference points		1.5	ns
t_{p_d1_skew}	DMD data skew – DMD_D(14:0), DMD_SCTRL, DMD_LOADB, and DMD_TRC signals relative to each other⁽³⁾	50% reference points		0.2	ns
t_{p_clk_skew}	Clock skew – DMD_DCLK and DMD_SAC_CLK relative to each other	50% reference points		0.2	ns
t_{p_d2_skew}	DAD/SAC data skew - DMD_SAC_BUS, DMD_DRC_OEZ⁽⁶⁾, DMD_DRC_BUS, and DMD_DRC_STRB signals relative to DMD_SAC_CLK	50% reference points		0.2	ns

(1) This range includes the 200 ppm of the external oscillator (but no jitter).

(2) Assumes minimum DMD setup time = 1 ns and minimum DMD hold time = 1 ns

(3) Assumes DMD data routing skew = 0.1 ns max

(4) Output setup and hold numbers already account for controller clock jitter. Only routing skew and DMD setup/hold must be considered in system timing analysis.

(5) Assumes a 30-Ω series termination for all DMD interface signals (except DAD_DMD_OEZ)

(6) DMD_DAD_OEZ requires a 30- to 100-kΩ external pullup resistor connected to VCC18 to achieve proper timing.