7.3.1 Parallel Bus Interface

The parallel bus interface complies with standard graphics interface protocol, which includes a vertical sync signal (VSYNC_WE), horizontal sync signal (HSYNC_CS), optional data valid signal (DATAEN_CMD), a 24-bit data bus (PDATA), and a pixel clock (PCLK). The user can program the polarity of both syncs and the active edge of the clock. Figure 1 shows the relationship of these signals. The data valid signal (DATAEN_CMD) is optional in that the DLPC2607 device provides auto-framing parameters that can be programmed to define the data valid window based on pixel and line counting relative to the horizontal and vertical syncs.

In addition to these standard signals, an optional side-band signal (PDM_CVS_TE) is available, which allows the user to stop the periodic frame updates without losing the displayed image. When PDM_CVS_TE is active, it acts as a data mask and does not allow the source image to be propagated to the display. A programmable PDM polarity parameter determines if it is active high or active low. This parameter defaults to make PDM_CVS_TE active high. Therefore, if this function is not desired, tie it to a logic low on the PCB. PDM_CVS_TE is restricted to change only during vertical blanking. Note that VSYNC_WE must remain active at all times (in Lock-to-VSYNC mode) or the display sequencer stops and causes the LEDs to be shut off.

The parallel bus interface supports six data transfer formats:

• 16-bit RGB565
• 18-bit RGB666
• 18-bit 4:4:4 YCrCb666
• 24-bit RGB888
• 24-bit 4:4:4 YCrCb888
• 16-bit 4:2:2 YCrCb (standard sampling assumed to be Y0Cb0, Y1Cr0, Y2Cb2, Y3Cr2, Y4Cb4, Y5Cr4, …)

Figure 9 shows the required PDATA(23:0) bus mapping for these six data transfer formats.

Figure 9. PDATA Bus – Parallel I/F Mode Bit Mapping