ZHCSC07E December   2013  – March 2019 DLPC2607

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Typical Current and Power Dissipation
    6. 6.6  I/O Characteristics
    7. 6.7  Internal Pullup and Pulldown Characteristics
    8. 6.8  Parallel I/F Frame Timing Requirements
    9. 6.9  Parallel I/F General Timing Requirements
    10. 6.10 Parallel I/F Maximum Parallel Interface Horizontal Line Rate
    11. 6.11 BT.656 I/F General Timing Requirements
    12. 6.12 100- to 120-Hz Operational Limitations
    13. 6.13 Flash Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 mDDR Memory Interface Timing Requirements
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Parallel Bus Interface
      2. 7.3.2 100- to 120-Hz 3-D Display Operation
    4. 7.4 Programming
      1. 7.4.1 Serial Flash Interface
      2. 7.4.2 Serial Flash Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 System Functional Modes
      2. 8.2.2 Design Requirements
        1. 8.2.2.1 Reference Clock
        2. 8.2.2.2 mDDR DRAM Compatibility
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Hot-Plug Usage
        2. 8.2.3.2 Maximum Signal Transition Time
        3. 8.2.3.3 Configuration Control
        4. 8.2.3.4 White Point Correction Light Sensor
      4. 8.2.4 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 System Power I/O State Considerations
    4. 9.4 Power-Up Initialization Sequence
    5. 9.5 Power-Good (PARK) Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  Internal ASIC PLL Power
      2. 10.1.2  General Handling Guidelines for Unused CMOS-Type Pins
      3. 10.1.3  SPI Signal Routing
      4. 10.1.4  mDDR Memory and DMD Interface Considerations
      5. 10.1.5  PCB Design
      6. 10.1.6  General PCB Routing (Applies to All Corresponding PCB Signals)
      7. 10.1.7  Maximum, Pin-to-Pin, PCB Interconnects Etch Lengths
      8. 10.1.8  I/F Specific PCB Routing
      9. 10.1.9  Number of Layer Changes
      10. 10.1.10 Stubs
      11. 10.1.11 Termination Requirements:
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 11.1.2 器件命名规则
        1. 11.1.2.1 器件标记
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 术语表
  12. 12机械、封装和可订购信息
    1. 12.1 封装选项附录
      1. 12.1.1 封装信息

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZVB|176
散热焊盘机械数据 (封装 | 引脚)

8.2.2.2 mDDR DRAM Compatibility

The following are the basic SDRAM compatibility requirements for the DLPC2607 SDRAM:

  • SDRAM memory type: mDDR
  • Size: 128 Mb minimum
  • Organization: N × 16-bits wide × 4 banks
  • Speed grade tCK: 6-ns max
  • CAS latency (CL), tRCD, tRP parameters (clocks): 3, 3, 3
  • Burst length options to include: Burst of 4
  • Refresh period (full device): ≥64 ms

The following mDDR DRAM devices are recommended for use with the DLPC2607 device:

Table 7. Compatible mDDR DRAM Device Options(6)(2)

DVT(1) VENDOR PART NUMBER SIZE (Mb) ORGANIZATION SPEED GRADE tCK(3) (ns) CL, tRCD, tRP (Clocks)
No Elpida EDK1216CFBJ-60-F (5) 128 8 M × 16 6 (1)
Yes Elpida EDD25163HBH-6ELS-F 256 16 M × 16 6 (1)
No Samsung K4X56163PL-FGC6 (4) 256 16 M × 16 6 (1)
Yes Samsung K4X56163PN-FGC6 256 16 M × 16 6 (1)
Yes Micron MT46H16M16LFBF-6IT:H 256 16 M × 16 6 (1)
Yes Hynix H5MS2562JFR-J3M 256 16 M × 16 6 (1)
(1) All these SDRAM devices appear compatible with the DLPC2607 device, but only those marked with 'yes' in the DVT column have been validated on a TI internal reference design board. Those marked with 'no' can be used at the risk of the ODM.
(2) These part numbers reflect Pb-free package.
(3) A 6-ns speed grade corresponds to a 166-MHz mDDR device.
(4) The manufacturer has issued an upcoming end of life notice on this device.
(5) These devices are EOL and no replacement with the same footprint. Do not use these in new designs.
(6) The DLPC2607 device does not use partial array self-refresh or temperature-compensated self-refresh options.
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