ZHCS244C January   2012  – August 2015 DLPC300

PRODUCTION DATA.  

1. 1 特性
2. 2 应用
3. 3 说明
4. 4 修订历史记录
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  ESD Ratings
   3. 6.3  Recommended Operating Conditions
   4. 6.4  Thermal Information
   5. 6.5  I/O Electrical Characteristics
   6. 6.6  Crystal Port Electrical Characteristics
   7. 6.7  Power Consumption
   8. 6.8  I2C Interface Timing Requirements
   9. 6.9  Parallel Interface Frame Timing Requirements
   10. 6.10 Parallel Interface General Timing Requirements
   11. 6.11 Parallel I/F Maximum Supported Horizontal Line Rate
   12. 6.12 BT.565 I/F General Timing Requirements
   13. 6.13 Flash Interface Timing Requirements
   14. 6.14 DMD Interface Timing Requirements
   15. 6.15 Mobile Dual Data Rate (mDDR) Memory Interface Timing Requirements
   16. 6.16 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
   4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Control
      2. 7.4.2 Parallel Bus Interface
      3. 7.4.3 BT.656 Interface
8. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
         1. 8.2.2.1 System Input Interfaces
            1. 8.2.2.1.1 Control Interface
         2. 8.2.2.2 Input Data Interface
         3. 8.2.2.3 System Output Interfaces
            1. 8.2.2.3.1 Illumination Interface
         4. 8.2.2.4 System Support Interfaces
            1. 8.2.2.4.1 Mobile DDR Synchronous Dram (MDDR)
            2. 8.2.2.4.2 Flash Memory Interface
            3. 8.2.2.4.3 DLPC300 Reference Clock
         5. 8.2.2.5 DMD Interfaces
            1. 8.2.2.5.1 DLPC300 to DLP3000 Digital Data
            2. 8.2.2.5.2 DLPC300 to DLP3000 Control Interface
            3. 8.2.2.5.3 DLPC300 to DLP3000 Micromirror Reset Control Interface
         6. 8.2.2.6 Maximum Signal Transition Time
   3. 8.3 System Examples
      1. 8.3.1 Video Source System Application
      2. 8.3.2 High Pattern Rate System With Optional Fpga
9. 9 Power Supply Recommendations
   1. 9.1 System Power-Up and Power-Down Sequence
      1. 9.1.1 Power Up Sequence
      2. 9.1.2 Power Down Sequence
      3. 9.1.3 Additional Power-Up Initialization Sequence Details
   2. 9.2 System Power I/O State Considerations
   3. 9.3 Power-Good (PARK) Support
10. 10Layout
    1. 10.1 Layout Guidelines
       1. 10.1.1 Printed Circuit Board Design Guidelines
       2. 10.1.2 Printed Circuit Board Layer Stackup Geometry
       3. 10.1.3 Signal Layers
       4. 10.1.4 Routing Constraints
       5. 10.1.5 Termination Requirements
       6. 10.1.6 PLL
       7. 10.1.7 General Handling Guidelines for Unused CMOS-Type Pins
       8. 10.1.8 Hot-Plug Usage
       9. 10.1.9 External Clock Input Crystal Oscillator
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
11. 11器件和文档支持
    1. 11.1 器件支持
       1. 11.1.1 Third-Party Products Disclaimer
       2. 11.1.2 器件命名规则
       3. 11.1.3 器件标记
    2. 11.2 文档支持
       1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
12. 12机械、封装和可订购信息