米6体育平台手机版

ZHCS244C January 2012 – August 2015 DLPC300

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

ZVB|176

散热焊盘机械数据 (封装 | 引脚)

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zhcs244c_oa

5 Pin Configuration and Functions

ZVB Package

176-Pin NFBGA

Bottom View

Pin Functions

PIN		I/O POWER	I/O TYPE	CLK SYSTEM	DESCRIPTION
NAME	NO.	I/O POWER	I/O TYPE	CLK SYSTEM	DESCRIPTION
SIGNALS
RESET	J14	VCC18	I₁	Async	DLPC300 power-on reset. Self configuration starts when a low-to-high transition is detected on this pin. All device power and clocks must be stable and within recommended operating conditions before this reset is deasserted. Note that the following 7 signals are high-impedance while RESET is asserted: DMD_PWR_EN, LEDDVR_ON, LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICS0 External pullups/pulldowns should be added as needed to these signals to avoid floating inputs where these signals are driven.
PARK	B8	VCC_ INTF	I₃	Async	DMD park control (active-low). Is set high to enable normal operation. PARK must be set high within 500 µs after releasing RESET. PARK must be set low a minimum of 500 µs before any power is to be removed from the DLPC300 or DLP3000. See System Power-Up/Power-Down Sequence for more details.
PLL_REFCLK_I	K15	VCC18 (filter)	I₄	N/A	Reference clock crystal input. If an external oscillator is used in place of a crystal, then this pin should be used as the oscillator input.
PLL_REFCLK_O	J15	VCC18 (filter)	O₁₄	N/A	Reference clock crystal return. If an external oscillator is used in place of a crystal, then this pin should be left unconnected (floating).
FLASH INTERFACE⁽¹⁾
SPICLK	A4	VCC_FLSH	O₂₄	N/A	SPI master clock output
SPIDIN	B4	VCC_FLSH	I₂	SPICLK	Serial data input from the external SPI slave FLASH device
SPICS0	A5	VCC_FLSH	O₂₄	SPICLK	SPI master chip select 0 output. Active-low
RESERVED	C6	VCC_FLSH	O₂₄	SPICLK	Not used. Reserved for future use. Should be left unconnected
SPIDOUT	C5	VCC_FLSH	O₂₄	SPICLK	Serial data output to the external SPI slave flash device. This pin sends address and control information as well as data when programming.
CONTROL
SCL	A10	VCC_ INTF	B₃₈	N/A	I²C clock. Bidirectional, open-drain signal. An external pullup is required. No I²C activity is permitted for a minimum of 100 ms after PARK and RESET are set high.
SDA	C10	VCC_ INTF	B₃₈	SCL	I²C data. Bidirectional, open-drain signal. An external pullup is required.
INIT_DONE	C9	VCC_ INTF	B₃₄	Async	Primary usage is to indicate when auto-initialization is complete, which is when INIT_DONE transitions high then low following release of RESET. INIT_DONE also helps flag a detected error condition in the form of a logic-high, pulsed interrupt flag.
PARALLEL RGB INTERFACE					PARALLEL RGB MODE		BT.656 I/F MODE
PCLK	D13	VCC_ INTF	I₃	N/A	Pixel clock⁽⁵⁾		Pixel clock⁽⁵⁾
PDM	H15	VCC_ INTF	B34	ASYNC	Not used, pulldown through an external resistor.		Not used, pulldown through an external resistor.
VSYNC	H14	VCC_ INTF	I₃	ASYNC	VSync⁽⁴⁾		Unused⁽³⁾
HSYNC	H13	VCC_ INTF	I₃	PCLK	HSync⁽⁴⁾		Unused⁽³⁾
DATEN	G15	VCC_ INTF	I₃	PCLK	Data valid⁽⁵⁾		Unused⁽³⁾
PDATA[0]	G14	VCC_ INTF	I₃	PCLK	Data0⁽²⁾		Data0⁽²⁾
PDATA[1]	G13	VCC_ INTF	I₃	PCLK	Data1⁽²⁾		Data1⁽²⁾
PDATA[2]	F15	VCC_ INTF	I₃	PCLK	Data2⁽²⁾		Data2⁽²⁾
PDATA[3]	F14	VCC_ INTF	I₃	PCLK	Data3⁽²⁾		Data3⁽²⁾
PDATA[4]	F13	VCC_ INTF	I₃	PCLK	Data4⁽²⁾		Data4⁽²⁾
PDATA[5]	E15	VCC_ INTF	I₃	PCLK	Data5⁽²⁾		Data5⁽²⁾
PDATA[6]	E14	VCC_ INTF	I₃	PCLK	Data6⁽²⁾		Data6⁽²⁾
PDATA[7]	E13	VCC_ INTF	I₃	PCLK	Data7⁽²⁾		Data7⁽²⁾
PDATA[8]	D15	VCC_ INTF	I₃	PCLK	Data8⁽²⁾		Unused⁽³⁾
PDATA[9]	D14	VCC_ INTF	I₃	PCLK	Data9⁽²⁾		Unused⁽³⁾
PDATA[10]	C15	VCC_ INTF	I₃	PCLK	Data10⁽²⁾		Unused⁽³⁾
PDATA[11]	C14	VCC_ INTF	I₃	PCLK	Data11⁽²⁾		Unused⁽³⁾
PDATA[12]	C13	VCC_ INTF	I₃	PCLK	Data12⁽²⁾		Unused⁽³⁾
PDATA[13]	B15	VCC_ INTF	I₃	PCLK	Data13⁽²⁾		Unused⁽³⁾
PDATA[14]	B14	VCC_ INTF	I₃	PCLK	Data14⁽²⁾		Unused⁽³⁾
PDATA[15]	A15	VCC_ INTF	I₃	PCLK	Data15⁽²⁾		Unused⁽³⁾
PDATA[16]	A14	VCC_ INTF	I₃	PCLK	Data16⁽²⁾		Unused⁽³⁾
PDATA[17]	B13	VCC_ INTF	I₃	PCLK	Data17⁽²⁾		Unused⁽³⁾
PDATA[18]	A13	VCC_ INTF	I₃	PCLK	Data18⁽²⁾		Unused⁽³⁾
PDATA[19]	C12	VCC_ INTF	I₃	PCLK	Data19⁽²⁾		Unused⁽³⁾
PDATA[20]	B12	VCC_ INTF	I₃	PCLK	Data20⁽²⁾		Unused⁽³⁾
PDATA[21]	A12	VCC_ INTF	I₃	PCLK	Data21⁽²⁾		Unused⁽³⁾
PDATA[22]	C11	VCC_ INTF	I₃	PCLK	Data22⁽²⁾		Unused⁽³⁾
PDATA[23]	B11	VCC_ INTF	I₃	PCLK	Data23⁽²⁾		Unused⁽³⁾
DMD INTERFACE
DMD_D0	M15	VCC18	O₅₈	DMD_DCLK	DMD data pins. DMD data pins are double data rate (DDR) signals that are clocked on both edges of DMD_DCLK. All 15 DMD data signals are use to interface to the DLP3000.
DMD_D1	N14
DMD_D2	M14
DMD_D3	N15
DMD_D4	P13
DMD_D5	P14
DMD_D6	P15
DMD_D7	R15
DMD_D8	R12
DMD_D9	N11
DMD_D10	P11
DMD_D11	R11
DMD_D12	N10
DMD_D13	P10
DMD_D14	R10
DMD_DCLK	N13	VCC18	O₅₈	N/A	DMD data clock (DDR)
DMD_LOADB	R13	VCC18	O₅₈	DMD_DCLK	DMD data load signal (active-low). This signal requires an external pullup to VCC18.
DMD_SCTRL	R14	VCC18	O₅₈	DMD_DCLK	DMD data serial control signal
DMD_TRC	P12	VCC18	O₅₈	DMD_DCLK	DMD data toggle rate control
DMD_DRC_BUS	L13	VCC18	O₅₈	DMD_SAC_CLK	DMD reset control bus data
DMD_DRC_STRB	K13	VCC18	O₅₈	DMD_SAC_CLK	DMD reset control bus strobe
DMD_DRC_OE	M13	VCC18	O₅₈	Async	DMD reset control enable (active-low). This signal requires an external pullup to VCC18.
DMD_SAC_BUS	L15	VCC18	O₅₈	DMD_SAC_CLK	DMD stepped-address control bus data
DMD_SAC_CLK	L14	VCC18	O₅₈	N/A	DMD stepped-address control bus clock
DMD_PWR_EN	K14	VCC18	O₁₄	Async	DMD power regulator enable (active-high). This is an active-high output that should be used to control DMD V_OFFSET, V_BIAS, and V_RESETvoltages. DMD_PWR_EN is driven high as a result of the PARK input signal being set high. However, DMD_PWR_EN is held high for 500 µs after the PARK input signal is set low before it is driven low. A weak external pulldown resistor is recommended to keep this signal at a known state during power-up reset.
SDRAM INTERFACE
MEM_CLK_P	D1	VCC18	O₇₄	N/A	mDDR memory, differential memory clock
MEM_CLK_N	E1	VCC18	O₇₄	N/A	mDDR memory, differential memory clock
MEM_A0	P1	VCC18	O₆₄	MEM_CLK	mDDR memory, multiplexed row and column address
MEM_A1	R3
MEM_A2	R1
MEM_A3	R2
MEM_A4	A1
MEM_A5	B1
MEM_A6	A2
MEM_A7	B2
MEM_A8	D2
MEM_A9	A3
MEM_A10	P2
MEM_A11	B3
MEM_A12	D3
MEM_BA0	M3	VCC18	O₆₄	MEM_CLK	mDDR memory, bank select
MEM_BA1	P3	VCC18	O₆₄	MEM_CLK	mDDR memory, bank select
MEM_RAS	P4	VCC18	O₆₄	MEM_CLK	mDDR memory, row address strobe (active-low)
MEM_CAS	R4	VCC18	O₆₄	MEM_CLK	mDDR memory, column address strobe (active-low)
MEM_WE	R5	VCC18	O₆₄	MEM_CLK	mDDR memory, write enable (active-low)
MEM_CS	J3	VCC18	O₆₄	MEM_CLK	mDDR memory, chip select (active-low)
MEM_CKE	C1	VCC18	O₆₄	MEM_CLK	mDDR memory, clock enable (active-high)
MEM_LDQS	J2	VCC18	B₆₄	N/A	mDDR memory, lower byte, R/W data strobe
MEM_LDM	J1	VCC18	O₆₄	MEM_LDQS	mDDR memory, lower byte, write data mask
MEM_UDQS	G1	VCC18	B₆₄	N/A	mDDR memory, upper byte, R/W data strobe
MEM_UDM	H1	VCC18	O₆₄	MEM_UDQS	mDDR memory, upper byte, write data mask
MEM_DQ0	N1	VCC18	B₆₄	MEM_LDQS	mDDR memory, lower byte, bidirectional R/W data
MEM_DQ1	M2
MEM_DQ2	M1
MEM_DQ3	L3
MEM_DQ4	L2
MEM_DQ5	K2
MEM_DQ6	L1
MEM_DQ7	K1
MEM_DQ8	H2	VCC18	B₆₄	MEM_UDQS	mDDR memory, upper byte, bidirectional R/W data
MEM_DQ9	G2
MEM_DQ10	H3
MEM_DQ11	F3
MEM_DQ12	F1
MEM_DQ13	E2
MEM_DQ14	F2
MEM_DQ15	E3
LED DRIVER INTERFACE
RPWM	N8	VCC18	O₁₄	Async	Red LED PWM signal used to control the LED current⁽⁶⁾.
GPWM	P9	VCC18	O₁₄	Async	Green LED PWM signal used to control the LED current⁽⁶⁾.
BPWM	R8	VCC18	O₁₄	Async	Blue LED PWM signal used to control the LED current⁽⁶⁾.
LED_SEL_0	R6	VCC18	O₁₄	Async	LED enable SELECT. Controlled by DMD sequence timing.
						LED_SEL(1:0)	Selected LED
						00	None
						01	Red
LED_SEL_1	N6					10	Green
						11	Blue
					A decode circuit is required to decode the selected LED enable.
LEDDRV_ON	P7	VCC18	O₁₄	Async	LED driver master enable. Active-high output control to external LED driver logic. This signal is driven high 100 ms after LED_ENABLE is driven high. Driven low immediately when either LED_ENABLE or PARK is driven low.
LED_ENABLE	A11	VCC_ INTF	I₃	Async	LED enable (active-high input). A logic low on this signal forces LEDDRV_ON low and LED_SEL(1:0) = 00b. These signals are enabled 100 ms after LED_ENABLE transitions from low to high.
RED_EN	B5	VCC18	B₁₈	Async	When not used with an optional FPGA, this signal should be connected to the RED LED enable circuit. When RED_EN is high, the red LED is enabled. When RED_EN is low, the red LED is disabled. When used with the optional FPGA, this signal should be pulled down to ground through an external resistor. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I²C LED Enable and Buffer Control register.
GREEN_EN	A7				When not used with an optional FPGA, this signal should be connected to the green LED enable circuit. When GREEN_EN is high, the green LED is enabled. When GREEN_EN is low, the green LED is disabled. When used with the optional FPGA, this signal should be pulled down to ground through an external resistor. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I²C LED Enable and Buffer Control register.
BLUE_EN	C8				When not used with an optional FPGA, this signal should be connected to the blue LED enable circuit. When BLUE_EN is high, the blue LED is enabled. When BLUE_EN is low, the blue LED is disabled. When used with the optional FPGA, this signal should be pulled down to ground through an external resistor. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I²C LED Enable and Buffer Control register.
WHITE POINT CORRECTION LIGHT SENSOR I/F
CMP_OUT	A6	VCC18	I₁	Async	Successive approximation ADC comparator output (DLPC300 input). Assumes a successive approximation ADC is implemented with a light sensor and/or thermocouple feeding one input of an external comparator and the other side of the comparator driven from the DLPC300 CMP_PWM pin. If not used, this signal should be pulled down to ground.
CMP_PWM	B7	VCC18	O₁₄	Async	Successive approximation comparator pulse-duration modulation input. Supplies a PWM signal to drive the successive approximation ADC comparator used in light-to-voltage light sensor applications. Should be left unconnected if this function is not used.
CMP_PWR	P5	VCC18	B₁₄	Async	Power control signal for the WPC light sensor and other analog support circuits using the DLPC300 ADC. Alternatively, it provides general-purpose I/O to the WPC microprocessor internal to the DLPC300. Should be left unconnected if not used.
TRIGGER CONTROL
OUTPUT_TRIGGER	N9	VCC18	B₁₈	Async	Trigger output. Indicates that a pattern or image is displayed on the screen and is ready to be captured. With an optional FPGA, this signal is connected to the FPGA trigger input. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I²C LED Enable and Buffer Control register. If not used, this signal should be pulled down to ground through an external resistor.
PATTERN CONTROL
PATTERN_INVERT	C7	VCC18	B₁₈	Async	Inverts the current 1-bit pattern held in the DLPC300 buffer. When used with an optional FPGA, this signal should be connected to DMC_TRC of the FPGA. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I²C LED Enable and Buffer Control register. If not used, this signal should be pulled down to ground through an external resistor.
OPTIONAL FPGA BUFFER MANAGEMENT INTERFACES
RD_BUF0	B6	VCC18	B₁₈	Async	When not used with an optional FPGA, this signal should be pulled down to ground through an external resistor. When used with an optional FPGA, this signal should be connected to RD_PTR_SDC[0] of the FPGA. RD_BUFF1 and RD_BUFF0 indicate to the FPGA one of the four buffers currently in use. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I²C LED Enable and Buffer Control register.
RD_BUF1/I2C_ADDR_SEL	R9				This signal is sampled when RESET is deasserted to choose between two predefined 7-bit I²C slave addresses. If I2C_ADDR_SEL signal is pulled-low, then the DLPC300's I²C slave address is 1Bh. If I2C_ADDR_SEL signal is pulled-high, then the DLPC300's I²C slave address is 1Dh. When used with an optional FPGA, this signal should be connected to RD_PTR_SDC[1] of the FPGA. RD_BUFF1 and RD_BUFF0 indicate to the FPGA one of the four buffers currently in use. This signal is set to input upon deassertion of RESET and configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I²C LED Enable and Buffer Control register.
BUFFER_SWAP	A8				When not used with an optional FPGA, this signal should be pulled down to ground through an external resistor. When used with an optional FPGA, this signal should be connected to BUFF_SWAP_SEQ of the FPGA. BUFFER_SWAP indicates to the FPGA when to advance the buffer. This signal is configured as output and driven low when the DLPR300 serial flash PROM is loaded by the DLPC300, but the signal is not enabled. To enable this output, a write to I²C LED Enable and Buffer Control register.
CONTROLLER MANUFACTURER TEST SUPPORT
TEST_EN	A9	VCC_INTF	I₃	N/A	Reserved for test. Should be connected directly to ground on the PCB for normal operation. Includes weak internal pulldown
BOARD LEVEL TEST AND DEBUG
JTAGTDI	P6	VCC18	I₁	JTAGTCK	JTAG, serial data in. Includes weak internal pullup
JTAGTCK	N5	VCC18	I₁	N/A	JTAG, serial data clock. Includes weak internal pullup
JTAGTMS	N7	VCC18	I₁	JTAGTCK	JTAG, test mode select. Includes weak internal pullup
JTAGTDO	R7	VCC18	I₁₄	JTAGTCK	JTAG, serial data out
JTAGRST	P8	VCC18	I₁	ASYNC	JTAG, RESET (active-low). Includes weak internal pullup. This signal must be tied to ground, through an external 15-kΩ or less resistor for normal operation.

(1) Each device connected to the SPI bus must operate from VCC_FLSH.

(2) PDATA[23:0] bus mapping is pixel-format and source-mode dependent. See later sections for details.

(3) Unused inputs should be pulled down to ground through an external resistor.

(4) VSYNC, HSYNC and data valid polarity is software programmable.

(5) Pixel clock capture edge is software programmable.

(6) All LED PWM signals are forced high when LEDDRV_ON = 0, SW LED control is disabled, or the sequence stops.

Pin Functions — Power and Ground⁽¹⁾

POWER GROUP	PIN NUMBERS	DESCRIPTION
VDD10	D5, D9, F4, F12, J4, J12, M6, M8, M11	1-V core logic power supply (9)
VDD_PLL	H12	1-V power supply for the internal PLL (1)
VCC18	C4, D8, E4, G3, K3, K12, L4, M5, M9, M12, N4, N12	1.8-V power supply for all I/O other than the host/ video interface and the SPI flash buses (12)
VCC_FLSH	D6	1.8- , 2.5- or 3.3-V power supply for SPI flash bus I/O (1)
VCC_INTF	D11, E12	1.8- , 2.5- or 3.3-V power supply for all I/Os on the host/video interface (includes I²C, PDATA, video syncs, PARK and LED_ENABLE pins) (2)
GND	D4, D7, D10, D12, G4, G12, H4, K4, L12, M4, M7, M10	Common ground (12)
RTN_PLL	J13	Analog ground return for the PLL (This should be connected to the common ground GND through a ferrite (1)
Reserved	B9, C2, C3, C6, N2, N3
Reserved	B10	This pin must be pulled up to VCC_INTF

(1) 132 total signal I/O pins, 38 total power/ground pins, 7 total reserved pins