(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS (ground).

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(1) VCCIO represents the actual supply voltage applied to the corresponding I/O.

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

(1) This table lists the typical current and power consumption of the individual supplies. Note that VCC_FLSH power is 0 because the serial flash is only accessed upon device configuration and not during normal operation.

(1) Total horizontal blanking is driven by the maximum line rate for a given source, which is a function of resolution and orientation. See Parallel I/F Maximum Supported Horizontal Line Rate for the maximum line rate for each source/display combination. t_{p_thb} = Roundup[(1000 × ƒ_clock) / LR] – APPL where ƒ_clock = Pixel clock rate in MHz, LR = Line rate in kHz, and APPL is the number of active pixels per (horizontal) line. If t_{p_thb} is calculated to be less than t_{p_hbp} + t_{p_hfp}, then the pixel clock rate is too low or the line rate is too high and one or both must be adjusted.

(2) The programmable parameter Vertical Sync Line Delay (I²C: 0x23) must be set such that: 6 – Vertical Front Porch (t_{p_vfp}) (min 0) ≤ Vertical Sync Line Delay ≤ Vertical Back Porch (t_{p_vbp}) – 2 (max 15). The default value for Vertical Sync Line Delay is set to 5; thus, only a Vertical Back Porch less than 7 requires potential action.

(1) Clock jitter (in ns) should be calculated using this formula: Jitter = [1 / ƒ_clock – 28.35 ns]. Setup and hold times must be met during clock jitter.

(2) The active (capture) edge of PCLK for HSYNC, DATEN, and PDATA(23:0) is software programmable, but defaults to the rising edge.

(3) See Figure 3.

(1) See the DLPC300 Software Programmer's Guide (DLPU004) to invoke the appropriate input and output resolutions.

(2) NTSC and PAL are assumed to be interlaced sources.

(1) The BT.656 I/F accepts 8-bit per color, 4:2:2 YCb/Cr data encoded per the industry standard by PDATA(7:0) on the active edge of PCLK (that is, programmable) as shown in Figure 3.

(1) This range includes the 200 ppm of the external oscillator (but no jitter).

(2) Standard SPI protocol is to transmit data on the falling edge of SPICLK and to capture data on the rising edge. The DLPC300 does transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for SPI devices with long clock-to-Q timing. DLPC300 hold capture timing has been set to facilitate reliable operation with standard external SPI protocol devices.

(3) With the above output timing, DLPC300 provides the external SPI device 14-ns input setup and 14-ns input hold relative to the rising edge of SPICLK.

(1) This range includes the 200 ppm of the external oscillator (but no jitter).

(2) Assumes minimum DMD setup time = 1 ns and minimum DMD hold time = 1 ns

(3) Assumes DMD data routing skew = 0.1 ns max

(4) Output setup/hold numbers already account for controller clock jitter. Only routing skew and DMD setup/hold need be considered in system timing analysis.

(5) Assumes a 30-Ω series termination for all DMD interface signals

(1) Note that DQS must be within the t_DQSRS read data-skew window, but need not be centered.

(2) This includes the 200 ppm of the external oscillator (but no jitter).

(3) Output setup/hold numbers already account for controller clock jitter. Only routing skew and memory setup/hold must be considered in system timing analysis.

(4) Assumes a 30-Ω series termination on all signal lines

(5) CK and DQS pulse duration specifications for the DLPC300 assume it is interfacing to a 166-MHz mDDR device. Even though these memories are only operated at 133.33 MHz, according to memory vendors, the rated t_CK specification (that is, 6 ns) can be applied to determine minimum CK and DQS pulse duration requirements to the memory.

(1) Switching characteristics over Recommended Operating Conditions, C_L (minimum timing) = 5 pF, C_L (maximum timing) = 85 pF (unless otherwise noted).