ZHCS244C January   2012  – August 2015 DLPC300

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  I/O Electrical Characteristics
    6. 6.6  Crystal Port Electrical Characteristics
    7. 6.7  Power Consumption
    8. 6.8  I2C Interface Timing Requirements
    9. 6.9  Parallel Interface Frame Timing Requirements
    10. 6.10 Parallel Interface General Timing Requirements
    11. 6.11 Parallel I/F Maximum Supported Horizontal Line Rate
    12. 6.12 BT.565 I/F General Timing Requirements
    13. 6.13 Flash Interface Timing Requirements
    14. 6.14 DMD Interface Timing Requirements
    15. 6.15 Mobile Dual Data Rate (mDDR) Memory Interface Timing Requirements
    16. 6.16 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Configuration Control
      2. 7.4.2 Parallel Bus Interface
      3. 7.4.3 BT.656 Interface
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 System Input Interfaces
          1. 8.2.2.1.1 Control Interface
        2. 8.2.2.2 Input Data Interface
        3. 8.2.2.3 System Output Interfaces
          1. 8.2.2.3.1 Illumination Interface
        4. 8.2.2.4 System Support Interfaces
          1. 8.2.2.4.1 Mobile DDR Synchronous Dram (MDDR)
          2. 8.2.2.4.2 Flash Memory Interface
          3. 8.2.2.4.3 DLPC300 Reference Clock
        5. 8.2.2.5 DMD Interfaces
          1. 8.2.2.5.1 DLPC300 to DLP3000 Digital Data
          2. 8.2.2.5.2 DLPC300 to DLP3000 Control Interface
          3. 8.2.2.5.3 DLPC300 to DLP3000 Micromirror Reset Control Interface
        6. 8.2.2.6 Maximum Signal Transition Time
    3. 8.3 System Examples
      1. 8.3.1 Video Source System Application
      2. 8.3.2 High Pattern Rate System With Optional Fpga
  9. 9 Power Supply Recommendations
    1. 9.1 System Power-Up and Power-Down Sequence
      1. 9.1.1 Power Up Sequence
      2. 9.1.2 Power Down Sequence
      3. 9.1.3 Additional Power-Up Initialization Sequence Details
    2. 9.2 System Power I/O State Considerations
    3. 9.3 Power-Good (PARK) Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Printed Circuit Board Design Guidelines
      2. 10.1.2 Printed Circuit Board Layer Stackup Geometry
      3. 10.1.3 Signal Layers
      4. 10.1.4 Routing Constraints
      5. 10.1.5 Termination Requirements
      6. 10.1.6 PLL
      7. 10.1.7 General Handling Guidelines for Unused CMOS-Type Pins
      8. 10.1.8 Hot-Plug Usage
      9. 10.1.9 External Clock Input Crystal Oscillator
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 器件命名规则
      3. 11.1.3 器件标记
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ZVB|176
散热焊盘机械数据 (封装 | 引脚)
订购信息

9 Power Supply Recommendations

9.1 System Power-Up and Power-Down Sequence

Although the DLPC300 requires an array of power supply voltages, (for example, VDD, VDD_PLL, VCC_18, VCC_FLSH, VCC_INTF), there are no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC300. This is true for both power-up and power-down scenarios. Similarly, there is no minimum time between powering up or powering down the different supplies feeding the DLPC300. Note, however, that it is not uncommon for there to be power-sequencing requirements for the devices that share the supplies with the DLPC300.

Although there is no risk of damaging the DLPC300 as a result of a given power sequence, from a functional standpoint, there is one specific power-sequencing recommendation to ensure proper operation. In particular, all controller power should be applied and allowed to reach minimum specified voltage levels before RESET is deasserted to ensure proper power-up initialization is performed. All I/O power should remain applied as long as 1-V core power is applied and RESET is deasserted.

Note that when VDD10 core power is applied but I/O power is not applied, additional leakage current may be drawn.

DLPC300 PU_PD_tim_lps023.gif Figure 17. Power-Up/Down Timing

9.1.1 Power Up Sequence

To minimize leakage currents and ensure proper operation, apply the following power up sequence. These steps are numbered in green with a circle around the step number in Figure 17.

  1. Apply power to VDD10 and VDD_PLL while driving RESET low
  2. After VDD10 power has reached minimum operating voltage, apply power to VCC18, VCC_INTF, and VCC_FLSH
  3. After VCC18, VCC_INTF, and VCC_FLSH have reached minimum operating voltage, wait for the reference clock to stabilize (PLL_REFCLK). The time for the clock to stabilize depend on the external crystal or oscillator. Refer to the corresponding crystal or oscillator data sheet for appropriate time
  4. Once the reference clock is stable, release reset to DLPC300 by driving RESET high. GPIO4_INTF will be driven high by the DLPC300 to indicate that Auto-Initialization is Busy
  5. Drive PARK high within 500usec after RESET is driven high
  6. Wait for DLPC300 to drive GPIO4_INTF low ( a minimum of 100 ms) to indicate that the DLPC300 has completed the auto-Initialization and the device is ready to accept I2C commands

9.1.2 Power Down Sequence

To minimize leakage currents and ensure proper operation, apply the following power down sequence. These steps are numbered in red with a square around the step number in Figure 17.

  1. Drive PARK low. This starts the park sequence which takes a maximum of 500 usec
  2. Wait a minimum of 500 usec after driving PARK low before driving RESET low
  3. Wait for DLPC300 to drive DMD_PWR_EN low before removing power to VCC_INTF and VCC_FLSH
  4. Wait a minimum of 100 ms after DLPC300 drives DMD_PWR_EN low before removing power to VCC18
  5. Once power has been removed from VCC18, remove power to VDD10 and VDD_PLL

9.1.3 Additional Power-Up Initialization Sequence Details

It is assumed that an external power monitor holds the DLPC300 in system reset during power-up. It must do this by driving RESET to a logic-low state. It should continue to assert system reset until all controller voltages have reached minimum specified voltage levels, PARK is asserted high, and input clocks are stable. During this time, most controller outputs are driven to an inactive state and all bidirectional signals are configured as inputs to avoid contention. Controller outputs that are not driven to an inactive state are in the high-impedance state. These include DMD_PWR_EN, LEDDVR_ON, LED_SEL_0, LED_SEL_1, SPICLK, SPIDOUT, and SPICS0. After power is stable and the PLL_REFCLK clock input to the DLPC300 is stable, then RESET should be deactivated (set to a logic high). The DLPC300 then performs a power-up initialization routine that first locks its PLL followed by loading self-configuration data from the external flash. On release of RESET, all DLPC300 I/Os become active. Immediately following the release of RESET, the INIT_BUSY signal is driven high to indicate that the auto-initialization routine is in progress. On completion of the auto-initialization routine, the DLPC300 drives INIT_BUSY low to signal INITIALIZATION DONE.

Note that the host processor can start sending standard I2C commands after INIT_BUSY goes low, or a 100-ms timer expires in the host processor, whichever is earlier.

See Figure 18 for a visualization of this sequence.

DLPC300 ini_timeline_lps023.gif Figure 18. Initialization Timeline

9.2 System Power I/O State Considerations

Note that:

  • If VCC18 I/O power is applied when VDD10 core power is not applied, then all mDDR (non fail-safe) and non-mDDR (fail-safe) output signals associated with the VCC18 supply are in a high-impedance state.
  • If VCC_INTF or VCC_FLSH I/O power is applied when VDD10 core power is not applied, then all output signals associated with these inactive I/O supplies are in a high-impedance state.
  • If VDD10 core power is applied but VCC_INTF or VCC_FLSH I/O power is not applied, then all output signals associated with these inactive I/O supplies are in a high-impedance state.
  • If VDD10 core power is applied but VCC18 I/O power is not applied, then all mDDR (non fail-safe) and non-mDDR (fail-safe) output signals associated with the VCC18 I/O supply are in a high-impedance state; however, if driven high externally, only the non-mDDR (fail-safe) output signals remain in a high-impedance state, and the mDDR (non fail-safe) signals are shorted to ground through clamping diodes.

9.3 Power-Good (PARK) Support

The PARK signal is defined to be an early warning signal that should alert the controller 500 µs before dc supply voltages have dropped below specifications. This allows the controller time to park the DMD, ensuring the integrity of future operation. Note that the reference clock should continue to run and RESET should remain deactivated for at least 500 µs after PARK has been deactivated (set to a logic low) to allow the park operation to complete.

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