ZHCSCU2E February 2014 – November 2020 DLPC3433 , DLPC3438
PRODUCTION DATA
The DLPC34xx controller DMD interface consists of a HS 1.8-V sub-LVDS output only interface with a maximum clock speed of 600-MHz DDR and a LS SDR (1.8-V LVCMOS) interface with a fixed clock speed of 120 MHz. The DLPC34xx sub-LVDS interface supports a number of DMD display sizes, and as a function of resolution, not all output data lanes are needed as DMD display resolutions decrease in size. With internal software selection, the DLPC34xx also supports a limited number of DMD interface swap configurations that can help board layout by remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 7-9 shows the four options available for the DLP3010 (.3 720p) DMD specifically.
| DLPC34xx Controller 8 LANE DMD ROUTING OPTIONS | DMD PINS | |||
|---|---|---|---|---|
| OPTION 1 | OPTION 2 | |||
| HS_WDATA_D_P HS_WDATA_D_N |
HS_WDATA_E_P HS_WDATA_E_N |
Input DATA_p_0 Input DATA_n_0 |
||
| HS_WDATA_C_P HS_WDATA_C_N |
HS_WDATA_F_P HS_WDATA_F_N |
Input DATA_p_1 Input DATA_n_1 |
||
| HS_WDATA_B_P HS_WDATA_B_N |
HS_WDATA_G_P HS_WDATA_G_N |
Input DATA_p_2 Input DATA_n_2 |
||
| HS_WDATA_A_P HS_WDATA_A_N |
HS_WDATA_H_P HS_WDATA_H_N |
Input DATA_p_3 Input DATA_n_3 |
||
| HS_WDATA_H_P HS_WDATA_H_N |
HS_WDATA_A_P HS_WDATA_A_N |
Input DATA_p_4 Input DATA_n_4 |
||
| HS_WDATA_G_P HS_WDATA_G_N |
HS_WDATA_B_P HS_WDATA_B_N |
Input DATA_p_5 Input DATA_n_5 |
||
| HS_WDATA_F_P HS_WDATA_F_N |
HS_WDATA_C_P HS_WDATA_C_N |
Input DATA_p_6 Input DATA_n_6 |
||
| HS_WDATA_E_P HS_WDATA_E_N |
HS_WDATA_D_P HS_WDATA_D_N |
Input DATA_p_7 Input DATA_n_7 |
||
The sub-LVDS high-speed interface waveform quality and timing on the DLPC34xx controller depends on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control and Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements.