ZHCSIG4B July   2018  – October 2020 DLPC3434

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1. 5.1 Test Pins and General Control
    2. 5.2 Parallel Port Input
    3. 5.3 DSI Input Data and Clock
    4. 5.4 DMD Reset and Bias Control
    5. 5.5 DMD Sub-LVDS Interface
    6. 5.6 Peripheral Interface
    7. 5.7 GPIO Peripheral Interface
    8. 5.8 Clock and PLL Support
    9. 5.9 Power and Ground
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 Flash Interface Timing Requirements
    15. 6.15 Other Timing Requirements
    16. 6.16 DMD Sub-LVDS Interface Switching Characteristics
    17. 6.17 DMD Parking Switching Characteristics
    18. 6.18 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Source Requirements
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 Parallel Interface Data Transfer Format
        3. 7.3.1.3 3D Display
      2. 7.3.2 Device Startup
      3. 7.3.3 SPI Flash
        1. 7.3.3.1 SPI Flash Interface
        2. 7.3.3.2 SPI Flash Programming
      4. 7.3.4 I2C Interface
      5. 7.3.5 Content Adaptive Illumination Control (CAIC)
      6. 7.3.6 Local Area Brightness Boost (LABB)
      7. 7.3.7 3D Glasses Operation
      8. 7.3.8 Test Point Support
      9. 7.3.9 DMD Interface
        1. 7.3.9.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
        2. 11.1.2.2 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Receiving Notification of Documentation Updates
    5. 11.5 Support Resources
    6. 11.6 Trademarks
  12. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Package Option Addendum
      1. 12.1.1 Packaging Information

封装选项

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6.5 Power Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER(1)(2)(3) TEST CONDITIONS MIN TYP(4) MAX(5) UNIT
I(VDD) + I(VDD_PLLM) + I(VDD_PLLD) 1.1-V rails(6) Frame rate = 50 Hz
Input = 1280 x 720 to FPGA		 177 283 mA
Frame rate = 60 Hz
Input = 1280 x 720 to FPGA		179289
I(VDD_PLLM)MCG PLL 1.1-V current(6)Frame rate = 50 Hz
Input = 1280 x 720 to FPGA		6mA
Frame rate = 60 Hz
Input = 1280 x 720 to FPGA		6
I(VDD_PLLD)DCG PLL 1.1-V current(6)Frame rate = 50 Hz
Input = 1280 x 720 to FPGA		6mA
Frame rate = 60 Hz
Input = 1280 x 720 to FPGA		6
I(VCC18)All 1.8-V I/O current: (1.8-V power supply for all I/O other than the host or parallel interface and the SPI flash interface)Frame rate = 50 Hz
Input = 1280 x 720 to FPGA		4967mA
Frame rate = 60 Hz
Input = 1280 x 720 to FPGA		4967
I(VCC_INTF)Host or parallel interface I/O current: 1.8 to 3.3 V (includes IIC0, PDATA, video syncs, and HOST_IRQ pins)Frame rate = 50 Hz
Input = 1280 x 720 to FPGA		2mA
Frame rate = 60 Hz
Input = 1280 x 720 to FPGA		2
I(VCC_FLSH)Flash interface I/O current: 1.8 to 3.3 VFrame rate = 50 Hz
Input = 1280 x 720 to FPGA		1mA
Frame rate = 60 Hz
Input = 1280 x 720 to FPGA		1
(1) Values assume all pins using 1.1 V are tied together (including VDDLP12), and programmable host and flash I/O are at the minimum nominal voltage (that is 1.8 V).
(2) Input image is 1280 × 720 (720p) 24 bits using reduced VESA timings on the parallel interface at the frame rate shown with the 0.23-in HD (DLP230KP) DMD. The controller has the CAIC and LABB algorithms turned off.
(3) The values do not take into account software updates or customer changes that may affect power performance.
(4) Assumes nominal process, voltage, and temperature (25°C nominal ambient) with nominal input images.
(5) Assumes worst case process, maximum voltage, and high nominal ambient temperature of 65°C with worst case input image.
(6) This rail was not measured due to board limitations. Simulation values are used instead. Simulations assume 12.5% activity factor, 30% clock gating on appropriate domains, and mixed SVT (standard threshold voltage) or HVT (high threshold voltage) cells
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