米6体育平台手机版

ZHCSCM1F July 2014 – November 2020 DLPC3430 , DLPC3435

PRODUCTION DATA

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机械数据 (封装 | 引脚)

ZEZ|201
- MPBGAK7

散热焊盘机械数据 (封装 | 引脚)

6.15 DSI Host Timing Requirements

These timing requirements describe specific host minimum values that are higher than those specified in the MIPI standards. It is critical for proper operation that the host meet these minimum timing requirements for specified MIPI parameters. The decoded DSI data must also follow all Section 6.12.

			MIN	MAX	UNIT
Clock lane	Frequency		80	235	MHz
Data lane	Effective data rate		160	470	Mbps
Number of data lanes	Selectable		1	4	Lanes
t_HS-PREPARE+ t_HS-ZERO	During a LP to HS transition, the time that the transmitter drives the HS-0 state prior to transmitting the synchronization sequence	80 MHz to 94 MHz HS Clock	565		ns
t_HS-PREPARE+ t_HS-ZERO		95 MHz to 235 MHz HS Clock⁽¹⁾	465⁽²⁾		ns
t_HS-SETTLE	Time interval during which the HS receiver ignores any data lane HS transitions, starting from the beginning of T_HS-PREPARE; the HS receiver ignores any data lane transitions before the minimum value, and responds to any data lane transitions after the maximum value	80 MHz to 94 MHz HS Clock		565⁽³⁾	ns
t_HS-SETTLE		95 MHz to 235 MHz HS Clock		465⁽³⁾	ns

(1) Example: At 172 MHz and t_HS-PREPARE = 51.46 ns → 51.46 ns + t_HS-ZERO ≥ 465 ns. Therefore t_HS-ZERO≥= 413.54 ns.

(2) Minimum values are higher than those required by the MIPI standard. t_HS-PREPARE must be within the MIPI specified range.

(3) Maximum values are higher than those required by the MIPI standard.