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ZHCSCM1F July 2014 – November 2020 DLPC3430 , DLPC3435

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6.14 BT656 Interface General Timing Requirements

The DLPC34xx controller input interface supports the industry standard BT.656 parallel video interface. See the appropriate ITU-R BT.656 specification for detailed interface timing requirements. ⁽²⁾

			MIN	MAX	UNIT
ƒ_cll	PCLK frequency		1.0	33.5	MHz
t_{p_clkper}	PCLK period	50% reference points	29.85	1000	ns
t_{p_clkjit}	PCLK jitter	Max f_clock		See ⁽¹⁾
t_{p_wh}	PCLK pulse duration high	50% reference points	10.0		ns
t_{p_wl}	PCLK pulse duration low	50% reference points	10.0		ns
t_{p_su}	Setup time – PDATA(7:0) before the active edge of PCLK	50% reference points	3.0		ns
t_{p_h}	Hold time – PDATA(7:0) after the active edge of PCLK	50% reference points	0.9		ns
t_t	Transition time – all signals	20% to 80% reference points (rising signal) 80% to 20% reference points (falling signal)	0.2	3.0	ns

(1) Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒ_clock – 5.76 ns]. Clock jitter must maintain setup and hold times. BT.656 data bits must be mapped to the DLPC34xx PDATA bus as shown in Figure 6-9 shows BT.656 bus mode YCbCr 4:2:2 source PDATA (23:0) mapping.

(2) The BT.656 interface accepts 8-bits per color, 4:2:2 YCbCr data encoded per the industry standard through PDATA(7:0) on the active edge of PCLK. See Figure 6-9.

Figure 6-9 BT.656 Interface Mode Bit Mapping