The DLPC34xx controller supports the industry standard DSI (Display Serial Interface) Type-3 LVDS video interface with up to four lanes. DSI is a source-synchronous, high-speed, low-power, low-cost physical layer. The DSI-PHY unit receives data when it operates in high-speed (HS) mode. The DSI-PHY unit receives and transmits data when it operates in low-power (LP) mode for unidirectional data lanes. Point-to-point lane interconnect can be used for either data or clock signal transmission. The high-speed receiver is a differential line receiver circuit. The low-power receiver is an unterminated, single-ended receiver circuit. Figure 7-8 shows a high-level view of the DSI interface.

For a given frame rate, the DSI high-speed (HS) clock frequency must be fixed. If a different DSI clock frequency is ever needed (such as to support another frame rate), an I²C command must be sent to the controller with the updated HS clock frequency.

MIPI refers to the Mobile Industry Processor Interface standard.

Various DSI requirements and features of the DLPC34xx are as follows:

• compliant with the DSI-MIPI Specification for Display Serial Interface (V 1.02.00) except for those items noted in the DSI Host Timing Requirements table
• compliant with D-PHY standard MIPI Specification (V 1.0)
• MIPI DSI Type 3 architecture
• supports display resolutions from 320 × 200 to 1280 × 800
• supports video mode (command mode not supported)
• MIPI DCS^SM (Display Command Set^SM) commands sent over DSI not supported (send commands via I²C instead)
• supports multiple packets per transmission
• supports trigger messages in the forward direction
• data lanes configurable from one to four channels
• EOT (End of Transfer) command is supported and must be enabled
• CRC (cyclic redundancy check) and ECC (error correction code) for header supported
  • CRC and ECC can be disabled
• checksum for long packets with error reporting (but no ECC)
• supports one virtual channel for video mode
• supports burst mode
• supports non-burst with sync pulses and with sync event
• BTA (bus turn-around) mode not supported and must be disabled in the DSI host processor
• LP mode is required during vertical blanking and vertical sync. LP mode is not supported between pixel lines (i.e. HS blanking must be used for horizontal blanking and horizontal sync)
• an active DSI HS clock is required during LP blanking

- one clock lane

- one bi-directional data lane (Data0)

- up to three additional uni-directional data lanes (Data1, Data2, and Data3)

Figure 7-8 DSI High Level View

The differential DSI clock lane (DCLKN and DCLKP) must be in the LP11 (Idle) state upon the de-assertion of RESETZ (zero-to-one transition) and must remain in this state until HOST_IRQ is de-asserted (one-to-zero transition) to ensure proper DSI initialization.

The controller requires differential data lane '0' (DD0N:DD0P) for DSI operation. The three remaining data lanes are optional depending on the desired input resolution and frame rate. Not all display resolutions and frame rates are supported without using all four data lanes.

The state of GPIO (2:1) pins upon the de-assertion of RESETZ (zero-to-one transition) determines the number of DSI data lanes that are enabled for both LP and HS bus operation.