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ZHCSCM1F July 2014 – November 2020 DLPC3430 , DLPC3435

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6.16 Flash Interface Timing Requirements

The DLPC34xx flash memory interface consists of a SPI flash serial interface with a programmable clock rate. The DLPC34xx can support 1- to 128-Mb flash memories.⁽²⁾⁽³⁾⁽⁴⁾

			MIN	MAX	UNIT
f_clock	SPI_CLK frequency	See ⁽¹⁾	1.4	36.0	MHz
t_{p_clkper}	SPI_CLK period	50% reference points	27.8	704	ns
t_{p_wh}	SPI_CLK pulse duration high	50% reference points	352		ns
t_{p_wl}	SPI_CLK pulse duration low	50% reference points	352		ns
t_t	Transition time – all signals	20% to 80% reference points (rising signal) 80% to 20% reference points (falling signal)	0.2	3.0	ns
t_{p_su}	Setup time – SPI_DIN valid before SPI_CLK falling edge	50% reference points	10.0		ns
t_{p_h}	Hold time – SPI_DIN valid after SPI_CLK falling edge	50% reference points	0.0		ns
t_{p_clqv}	SPI_CLK clock falling edge to output valid time – SPI_DOUT and SPI_CSZ	50% reference points		1.0	ns
t_{p_clqx}	SPI_CLK clock falling edge output hold time – SPI_DOUT and SPI_CSZ	50% reference points	–3.0	3.0	ns

(1) This range include the ±200 ppm of the external oscillator (but no jitter).

(2) Standard SPI protocol is to transmit data on the falling edge of SPI_CLK and capture data on the rising edge. The DLPC34xx does transmit data on the falling edge, but it also captures data on the falling edge rather than the rising edge. This provides support for SPI devices with long clock-to-Q timing. DLPC34xx hold capture timing has been set to facilitate reliable operation with standard external SPI protocol devices.

(3) With the above output timing, DLPC34xx provides the external SPI device 8.2-ns input set-up and 8.2-ns input hold, relative to the rising edge of SPI_CLK.

(4) For additional requirements of the external flash device view the Section 7.3.3.1 section.

Figure 6-10 Flash Interface Timing