米6体育平台手机版

ZHCSJN9E january 2019 – april 2023 DLPC3436

PRODUCTION DATA

6.13 Parallel Interface General Timing Requirements

			MIN	MAX	UNIT
ƒ_clock	PCLK frequency		1.0	155.0	MHz
t_{p_clkper}	PCLK period	50% reference points	6.45	1000	ns
t_{p_clkjit}	PCLK jitter	Max ƒ_clock		See ⁽¹⁾
t_{p_wh}	PCLK pulse duration high	50% reference points	2.43		ns
t_{p_wl}	PCLK pulse duration low	50% reference points	2.43		ns
t_{p_su}	Setup time – HSYNC_CS, DATAEN_CMD, PDATA(23:0) valid before the active edge of PCLK	50% reference points	0.9		ns
t_{p_h}	Hold time – HSYNC_CS, DATAEN_CMD, PDATA(23:0) valid after the active edge of PCLK	50% reference points	0.9		ns
t_t	Transition time – all signals	20% to 80% reference points (rising signal) 80% to 20% reference points (falling signal)	0.2	2.0	ns
t_setup, 3DR	This is the setup time with respect to VSYNC⁽²⁾	50% reference points	1.0		ms
t_hold, 3DR	This is the hold time with respect VSYNC⁽³⁾	50% reference points	1.0		ms

(1) Calculate clock jitter (in ns) using this formula: Jitter = [1 / ƒ_clock – 5.76 ns]. Setup and hold times must be met even with clock jitter.

(2) In other words, the 3DR signal must change at least 1.0 ms before VSYNC changes.

(3) In other words, the 3DR signal must not change for at least 1.0 ms after VSYNC changes.

Figure 6-8 Parallel Interface Pixel Timing