ZHCSJN9E january 2019 – april 2023 DLPC3436
PRODUCTION DATA
The DLPC34x6 controller DMD interface consists of one high-speed (HS), 1.8-V sub-LVDS, output-only interface and one low speed (LS), 1.8-V LVCMOS SDR interface with a typical fixed clock speed of 120 MHz.