The parallel interface complies with standard graphics interface protocol, with the addition of the SUB_FRAME signal (which is a necessary output from the XC7Z020-1CLG484I4493 FPGA). The standard graphics interface protocol includes a vertical sync signal (VSYNC_WE), horizontal sync signal (HSYNC_CS), optional data valid signal (DATAEN_CMD), a 24-bit data bus (PDATA), and a pixel clock (PCLK). The polarity of both syncs and the active edge of the clock are programmable. Figure 6-7 shows the relationship of these signals.