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Figure 5-1 ZEZ Package201-Pin NFBGABottom View

Note: The lower image view is from the top.

Figure 5-2 13 mm × 13 mm Package – VF Ball Grid Array

Table 5-1 Test Pins and General Control

PIN		I/O	TYPE⁽⁴⁾	DESCRIPTION
NAME	NO.	I/O	TYPE⁽⁴⁾	DESCRIPTION
HWTEST_EN	C10	I	6	Manufacturing test enable signal. Connect this signal directly to ground on the PCB for normal operation.
PARKZ	C13	I	6	DMD fast park control (active low Input with a hysteresis buffer). This signal is used to quickly park the DMD when loss of power is imminent. The longest lifetime of the DMD may not be achieved with the fast park operation; therefore, this signal is intended to only be asserted when a normal park operation is unable to be completed. The PARKZ signal is typically provided from the DLPAxxxx interrupt output signal.
JTAGTCK	P12	I	6	TI internal use. Leave this pin unconnected.
JTAGTDI	P13	I	6	TI internal use. Leave this pin unconnected.
JTAGTDO1	N13⁽¹⁾	O	1	TI internal use. Leave this pin unconnected.
JTAGTDO2	N12⁽¹⁾	O	1	TI internal use. Leave this pin unconnected.
JTAGTMS1	M13	I	6	TI internal use. Leave this pin unconnected.
JTAGTMS2	N11	I	6	TI internal use. Leave this pin unconnected.
JTAGTRSTZ	P11	I	6	TI internal use. This pin must be tied to ground, through an external resistor for normal operation. Failure to tie this pin low during normal operation can cause start up and initialization problems.⁽²⁾
RESETZ	C11	I	6	Power-on reset (active low input with a hysteresis buffer). Self-configuration starts when a low-to-high transition is detected on RESETZ. All controller power and clocks must be stable before this reset is de-asserted. No signals are in their active state while RESETZ is asserted. This pin is typically connected to the RESET_Z pin of the DLPA300x.
TSTPT_0	R12	I/O	1	Test pins (includes weak internal pulldown). Pins are tri-stated while RESETZ is asserted low. Sampled as an input test mode selection control approximately 1.5 µs after de-assertion of RESETZ, and then driven as outputs.⁽²⁾⁽³⁾ Normal use: reserved for test output. Leave open for normal use. Note: An external pullup may put the DLPC34xx in a test mode. See Section 7.3.8 for more information.
TSTPT_1	R13	I/O	1
TSTPT_2	R14	I/O	1
TSTPT_3	R15	I/O	1
TSTPT_4	P14	I/O	1
TSTPT_5	P15	I/O	1
TSTPT_6	N14	I/O	1
TSTPT_7	N15	I/O	1

(1) If the application design does not require an external pullup, and there is no external logic that can overcome the weak internal pulldown resistor, then this I/O pin can be left open or unconnected for normal operation. If the application design does not require an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown is recommended to ensure a logic low.

(2) External resistor must have a value of 8 kΩ or less to compensate for pins that provide internal pullup or pulldown resistors.

(3) If the application design does not require an external pullup and there is no external logic that can overcome the weak internal pulldown, then the TSTPT I/O can be left open (unconnected) for normal operation. If operation does not call for an external pullup, but there is external logic that might overcome the weak internal pulldown resistor, then an external pulldown resistor is recommended to ensure a logic low.

(4) See Table 5-10 for type definitions.

Table 5-2 Parallel Port Input⁽¹⁾⁽²⁾

PIN		I/O	Type⁽⁴⁾	DESCRIPTION
NAME	NO.	I/O	Type⁽⁴⁾	PARALLEL RGB MODE
PCLK	P3	I	10	Pixel clock
PDM_CVS_TE	N4	I/O	5	Parallel data mask. Programable polarity with default of active high. Optional signal.
VSYNC_WE	P1	I	10	Vsync⁽³⁾
HSYNC_CS	N5	I	10	Hsync⁽³⁾
DATAEN_CMD	P2	I	10	Data valid
				(TYPICAL RGB 888)
PDATA_0 PDATA_1 PDATA_2 PDATA_3 PDATA_4 PDATA_5 PDATA_6 PDATA_7	K2 K1 L2 L1 M2 M1 N2 N1	I	10	Blue (bit weight 1) Blue (bit weight 2) Blue (bit weight 4) Blue (bit weight 8) Blue (bit weight 16) Blue (bit weight 32) Blue (bit weight 64) Blue (bit weight 128)
				(TYPICAL RGB 888)
PDATA_8 PDATA_9 PDATA_10 PDATA_11 PDATA_12 PDATA_13 PDATA_14 PDATA_15	R1 R2 R3 P4 R4 P5 R5 P6	I	10	Green (bit weight 1) Green (bit weight 2) Green (bit weight 4) Green (bit weight 8) Green (bit weight 16) Green (bit weight 32) Green (bit weight 64) Green (bit weight 128)
				(TYPICAL RGB 888)
PDATA_16 PDATA_17 PDATA_18 PDATA_19 PDATA_20 PDATA_21 PDATA_22 PDATA_23	R6 P7 R7 P8 R8 P9 R9 P10	I	10	Red (bit weight 1) Red (bit weight 2) Red (bit weight 4) Red (bit weight 8) Red (bit weight 16) Red (bit weight 32) Red (bit weight 64) Red (bit weight 128)
3DR	N6	I	10	3D reference For 3D applications: left or right 3D reference (left = 1, right = 0). To be provided by the host. Must transition in the middle of each frame (no closer than 1 ms to the active edge of VSYNC) If a 3D application is not used, pull this input low through an external resistor.

(1) PDATA(23:0) bus mapping depends on pixel format and source mode. See later sections for details.

(2) Connect unused inputs to ground or pulldown to ground through an external resistor (8 kΩ or less).

(3) VSYNC and HSYNC polarity can be adjusted by software.

(4) See Table 5-10 for type definitions.

Table 5-3 DSI Input Data and Clock

PIN		I/O	Type⁽¹⁾	DESCRIPTION
NAME	NO.	I/O	Type⁽¹⁾	DESCRIPTION
DCLKN DCLKP	E2 E1			Unused; leave unconnected and floating
DD0N DD0P DD1N DD1P DD2N DD2P DD3N DD3P	G2 G1 F2 F1 D2 D1 C2 C1
RREF	F3	—

(1) See Table 5-10 for type definitions.

Table 5-4 DMD Reset and Bias Control

PIN		I/O	TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	I/O	TYPE⁽¹⁾	DESCRIPTION
DMD_DEN_ARSTZ	B1	O	2	DMD driver enable (active high). DMD reset (active low). When corresponding I/O power is supplied, the controller drives this signal low after the DMD is parked and before power is removed from the DMD. If the 1.8-V power to the DLPC34xx is independent of the 1.8-V power to the DMD, then TI recommends including a weak, external pulldown resistor to hold the signal low in case DLPC34xx power is inactive while DMD power is applied.
DMD_LS_CLK	A1	O	3	DMD, low speed (LS) interface clock
DMD_LS_WDATA	A2	O	3	DMD, low speed (LS) serial write data
DMD_LS_RDATA	B2	I	6	DMD, low speed (LS) serial read data

(1) See Table 5-10 for type definitions.

Table 5-5 DMD Sub-LVDS Interface

PIN		I/O	TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	I/O	TYPE⁽¹⁾	DESCRIPTION
DMD_HS_CLK_P DMD_HS_CLK_N	A7 B7	O	4	DMD high speed (HS) interface clock
DMD_HS_WDATA_H_P DMD_HS_WDATA_H_N DMD_HS_WDATA_G_P DMD_HS_WDATA_G_N DMD_HS_WDATA_F_P DMD_HS_WDATA_F_N DMD_HS_WDATA_E_P DMD_HS_WDATA_E_N DMD_HS_WDATA_D_P DMD_HS_WDATA_D_N DMD_HS_WDATA_C_P DMD_HS_WDATA_C_N DMD_HS_WDATA_B_P DMD_HS_WDATA_B_N DMD_HS_WDATA_A_P DMD_HS_WDATA_A_N	A3 B3 A4 B4 A5 B5 A6 B6 A8 B8 A9 B9 A10 B10 A11 B11	O	4	DMD sub-LVDS high speed (HS) interface write data lanes. The true numbering and application of the DMD_HS_WDATA pins depend on the software configuration. See Table 7-9.

(1) See Table 5-10 for type definitions.

Table 5-6 Peripheral Interface⁽¹⁾

PIN		I/O	TYPE⁽³⁾	DESCRIPTION
NAME	NO.	I/O	TYPE⁽³⁾	DESCRIPTION
CMP_OUT	A12	I	6	Successive approximation ADC (analog-to-digital converter) comparator output (DLPC34xx Input). To implement, use a successive approximation ADC with a thermistor feeding one input of the external comparator and the DLPC34xx controller GPIO_10 (RC_CHARGE) pin driving the other side of the comparator. It is recommended to use the DLPAxxxx to achieve this function. CMP_OUT must be pulled-down to ground if this function is not used. (hysteresis buffer)
CMP_PWM	A15	O	1	TI internal use. Leave this pin unconnected.
HOST_IRQ⁽²⁾	N8	O	9	Host interrupt (output) HOST_IRQ indicates when the DLPC34xx auto-initialization is in progress and most importantly when it completes. This pin is tri-stated during reset. An external pullup must be included on this signal.
IIC0_SCL⁽⁴⁾	N10	I/O	7	I²C slave (port 0) SCL (bidirectional, open-drain signal with input hysteresis): This pin requires an external pullup resistor. The slave I²C I/Os are 3.6-V tolerant (high-voltage-input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I²C pullups must be connected to a host supply with an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage does not typically satisfy the V_IH specification of the slave I²C input buffers).
IIC1_SCL	R11	I/O	8	TI internal use. TI recommends an external pullup resistor.
IIC0_SDA⁽⁴⁾	N9	I/O	7	I²C slave (port 0) SDA. (bidirectional, open-drain signal with input hysteresis): This pin requires an external pullup resistor. The slave I²C port is the control port of controller. The slave I²C I/O pins are 3.6-V tolerant (high-volt-input tolerant) and are powered by VCC_INTF (which can be 1.8, 2.5, or 3.3 V). External I²C pullups must be connected to a host supply with an equal or higher supply voltage, up to a maximum of 3.6 V (a lower pullup supply voltage does not typically satisfy the V_IH specification of the slave I²C input buffers).
IIC1_SDA	R10	I/O	8	TI internal use. TI recommends an external pullup resistor.
LED_SEL_0	B15	O	1	LED enable select. Automatically controlled by the DLPC34xx programmable DMD sequence
LED_SEL_0	B15	O	1	LED_SEL(1:0) 00 01 10 11	Enabled LED None Red Green Blue
LED_SEL_1	B14	O	1	The controller drives these signals low when RESETZ is asserted and the corresponding I/O power is supplied. The controller continues to drive these signals low throughout the auto-initialization process. A weak, external pulldown resistor is recommended to ensure that the LEDs are disabled when I/O power is not applied.
SPI0_CLK	A13	O	13	SPI (Serial Peripheral Interface) port 0, clock. This pin is typically connected to the flash memory clock.
SPI0_CSZ0	A14	O	13	SPI port 0, chip select 0 (active low output). This pin is typically connected to the flash memory chip select. TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during controller reset assertion.
SPI0_CSZ1	C12	O	13	SPI port 0, chip select 1 (active low output). This pin typically remains unused. TI recommends an external pullup resistor to avoid floating inputs to the external SPI device during controller reset assertion.
SPI0_DIN	B12	I	12	Synchronous serial port 0, receive data in. This pin is typically connected to the flash memory data out.
SPI0_DOUT	B13	O	13	Synchronous serial port 0, transmit data out. This pin is typically connected to the flash memory data in.

(1) External pullup resistor must be 8 kΩ or less.

(2) For more information about usage, see Section 7.3.2.

(3) See Table 5-10 for type definitions.

(4) When VCC_INTF is powered and VDD is not powered, the controller may drive the IIC0_xxx pins low which prevents communication on this I²C bus. Do not power up the VCC_INTF pin before powering up the VDD pin for any system that has additional slave devices on this bus.

Table 5-7 GPIO Peripheral Interface⁽¹⁾

PIN		I/O	TYPE⁽¹⁾	DESCRIPTION⁽²⁾
NAME	NO.	I/O	TYPE⁽¹⁾	DESCRIPTION⁽²⁾
GPIO_19	M15	I/O	1	HBT_ODAT (Output): Required to be connected to the second DLPC3439 controller's HBT_IDAT (GPIO_17) input pin.
GPIO_18	M14	I/O	1	HBT_OCLK (Output): Required to be connected to the second DLPC3439 controller's HBT_ICLK (GPIO_16) input pin
GPIO_17	L15	I/O	1	HBT_IDAT (Input): Required to be connected to the second DLPC3439 controller's HBT_ODAT (GPIO_19) output pin
GPIO_16	L14	I/O	1	HBT_ICLK (Input): Required to be connected to the second DLPC3439 controller's HBT_OCLK (GPIO_18) outputpin.
GPIO_15	K15	I/O	1	DA_SYNC (BiDir): Required to be connected to the second DLPC3439 controller's DA_SYNC (GPIO_15) pin.
GPIO_14	K14	I/O	1	SEQ_SYNC (BiDir): Required to be connected to the second DLPC3439 controller's SEQ_SYNC (GPIO_14) pin with a 7.87k pullup resistor to VCC18.
GPIO_13	J15	I/O	1	General purpose I/O 13 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_12	J14	I/O	1	General purpose I/O 12 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_11	H15	I/O	1	General purpose I/O 11 (hysteresis buffer). Options: Thermistor power enable (output). Turns on the power to the thermistor when it is used and enabled. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_10	H14	I/O	1	General Purpose I/O 10 (hysteresis buffer). Options: RC_CHARGE (output): Intended to feed the RC charge circuit of the thermistor interface. Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_09	G15	I/O	1	General purpose I/O 09 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_08	G14	I/O	1	General purpose I/O 08 (hysteresis buffer). Normal mirror parking request (active low): To be driven by the PROJ_ON output of the host. A logic low on this signal causes the DLPC34xx to PARK the DMD, but it does not power down the DMD (the DLPAxxxx does that instead). The minimum high time is 200 ms. The minimum low time is 200 ms.
GPIO_07	F15	I/O	1	General purpose I/O 07 (hysteresis buffer). If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_06	F14	I/O	1	General purpose I/O 06 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_05	E15	I/O	1	General purpose I/O 05 (hysteresis buffer). Optional GPIO. If unused TI recommends this pin be configured as a logic zero GPIO output and left unconnected. Otherwise this pin requires an external pullup or pulldown to avoid a floating GPIO input.
GPIO_04	E14	I/O	1	MST_SLVZ (Input): Master or slave controller identifier signal (Master = 1, Slave = 0).
GPIO_03	D15	I/O	1	General purpose I/O 03 (hysteresis buffer). SPI1_CSZ0 (active low output): SPI1 chip select 0 signal. This pin is typically connected to the DLPAxxxx SPI_CSZ pin. Requires an external pullup resistor to deactivate this signal during reset and auto-initialization processes.
GPIO_02	D14	I/O	1	General purpose I/O 02 (hysteresis buffer). SPI1_DOUT (output): SPI1 data output signal. This pin is typically connected to the DLPAxxxx SPI_DIN pin.
GPIO_01	C15	I/O	1	General purpose I/O 01 (hysteresis buffer). SPI1_CLK (output): SPI1 clock signal. This pin is typically connected to the DLPAxxxx SPI_CLK pin.
GPIO_00	C14	I/O	1	General purpose I/O 00 (hysteresis buffer). SPI1_DIN (input): SPI1 data input signal. This pin is typically connected to the DLPAxxxx SPI_DOUT pin.

(1) GPIO pins must be configured through software for input, output, bidirectional, or open-drain operation. Some GPIO pins have one or more alternative use modes, which are also software configurable. An external pullup resistor is required for each signal configured as open-drain.

(2) General purpose I/O for the DLPC3439 controller. These GPIO pins are software configurable.

Table 5-8 Clock and PLL Support

PIN		I/O	TYPE⁽¹⁾	DESCRIPTION
NAME	NO.	I/O	TYPE⁽¹⁾	DESCRIPTION
PLL_REFCLK_I	H1	I	11	Reference clock crystal input. If an external oscillator is used instead of a crystal, use this pin as the oscillator input.
PLL_REFCLK_O	J1	O	5	Reference clock crystal return. If an external oscillator is used instead of a crystal, leave this pin unconnected (floating with no added capacitive load).

(1) See Table 5-10 for type definitions.

Table 5-9 Power and Ground

PIN		I/O	TYPE	DESCRIPTION
NAME	NO.	I/O	TYPE	DESCRIPTION
VDD	C5, D5, D7, D12, J4, J12, K3, L4, L12, M6, M9, D9, D13, F13, H13, L13, M10, D3, E3	—	PWR	Core 1.1-V power (main 1.1 V)
VDDLP12	C3	—	PWR	Reserved – tie to the VDD rail
VSS	C4, D6, D8, D10, E4, E13, F4, G4, G12, H4, H12, J3, J13, K4, K12, L3, M4, M5, M8, M12, G13, C6, C8, F6, F7, F8, F9, F10, G6, G7, G8, G9, G10, H6, H7, H8, H9, H10, J6, J7, J8, J9, J10, K6, K7, K8, K9, K10	—	GND	Core ground (eDRAM, I/O ground, thermal ground)
VCC18	C7, C9, D4, E12, F12, K13, M11	—	PWR	All 1.8-V I/O power: (1.8-V power supply for all I/O pins except the host or parallel interface and the SPI flash interface. This includes RESETZ, PARKZ, LED_SEL, CMP_OUT, GPIO, IIC1, TSTPT, and JTAG pins)
VCC_INTF	M3, M7, N3, N7	—	PWR	Host or parallel interface I/O power: 1.8 V to 3.3 V (Includes IIC0, PDATA, video syncs, and HOST_IRQ pins)
VCC_FLSH	D11	—	PWR	Flash interface I/O power: 1.8 V to 3.3 V (Dedicated SPI0 power pin)
VDD_PLLM	H2	—	PWR	MCG PLL (master clock generator phase lock loop) 1.1-V power
VSS_PLLM	G3	—	RTN	MCG PLL return
VDD_PLLD	J2	—	PWR	DCG PLL (DMD clock generator phase lock loop) 1.1-V power
VSS_PLLD	H3	—	RTN	DCG PLL return

Table 5-10 I/O Type Subscript Definition

I/O		SUPPLY REFERENCE	ESD STRUCTURE
SUBSCRIPT	DESCRIPTION	SUPPLY REFERENCE	ESD STRUCTURE
1	1.8-V LVCMOS I/O buffer with 8-mA drive	V_cc18	ESD diode to GND and supply rail
2	1.8-V LVCMOS I/O buffer with 4-mA drive	V_cc18	ESD diode to GND and supply rail
3	1.8-V LVCMOS I/O buffer with 24-mA drive	V_cc18	ESD diode to GND and supply rail
4	1.8-V sub-LVDS output with 4-mA drive	V_cc18	ESD diode to GND and supply rail
5	1.8-V, 2.5-V, 3.3-V LVCMOS with 4-mA drive	V_{cc_INTF}	ESD diode to GND and supply rail
6	1.8-V LVCMOS input	V_cc18	ESD diode to GND and supply rail
7	1.8-V, 2.5-V, 3.3-V I²C with 3-mA drive	V_{cc_INTF}	ESD diode to GND and supply rail
8	1.8-V I²C with 3-mA drive	V_cc18	ESD diode to GND and supply rail
9	1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive	V_{cc_INTF}	ESD diode to GND and supply rail
10	Reserved
11	1.8-V, 2.5-V, 3.3-V LVCMOS input	V_{cc_INTF}	ESD diode to GND and supply rail
12	1.8-V, 2.5-V, 3.3-V LVCMOS input	V_{cc_FLSH}	ESD diode to GND and supply rail
13	1.8-V, 2.5-V, 3.3-V LVCMOS with 8-mA drive	V_{cc_FLSH}	ESD diode to GND and supply rail

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5 Pin Configuration and Functions