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ZHCSI46C April 2018 – December 2020 DLPC3470

PRODUCTION DATA

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机械数据 (封装 | 引脚)

ZEZ|201
- MPBGAK7

散热焊盘机械数据 (封装 | 引脚)

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zhcsi46c_oa

7.3.10.1 Sub-LVDS (HS) Interface

The DLP2010LC and DLP2010NIR (.2 WVGA) DMDs do not require all of the available output data lanes of the controller. Internal software selection allows the controller to support multiple DMD interface swap configurations. These options can improve board layout by remapping specific combinations of DMD interface lines to other DMD interface lines as needed. Table 7-10 shows the four options available for the DLP2010LC DMD. Leave any unused DMD signal pairs unconnected on the final board design.

Table 7-10 DLP2010LC (.2 WVGA) DMD – Controller to 4-Lane DMD Pin Mapping Options

DLP2010LC 4-LANE DMD ROUTING OPTIONS				DMD PINS
OPTION 1	OPTION 2	OPTION 3	OPTION 4	DMD PINS
HS_WDATA_D_P HS_WDATA_D_N	HS_WDATA_E_P HS_WDATA_E_N	HS_WDATA_H_P HS_WDATA_H_N	HS_WDATA_A_P HS_WDATA_A_N	Input DATA_P_0 Input DATA_N_0
HS_WDATA_C_P HS_WDATA_C_N	HS_WDATA_F_P HS_WDATA_F_N	HS_WDATA_G_P HS_WDATA_G_N	HS_WDATA_B_P HS_WDATA_B_N	Input DATA_P_1 Input DATA_N_1
HS_WDATA_F_P HS_WDATA_F_N	HS_WDATA_C_P HS_WDATA_C_N	HS_WDATA_B_P HS_WDATA_B_N	HS_WDATA_G_P HS_WDATA_G_N	Input DATA_P_2 Input DATA_N_2
HS_WDATA_E_P HS_WDATA_E_N	HS_WDATA_D_P HS_WDATA_D_N	HS_WDATA_A_P HS_WDATA_A_N	HS_WDATA_H_P HS_WDATA_H_N	Input DATA_P_3 Input DATA_N_3

Figure 7-23 DLP2010LC (.2 WVGA) DMD Interface Example (Option 1 and 2)

The sub-LVDS high-speed interface waveform quality and timing on the DLPC34xx controller depends on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control and Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements.