ZHCSHY3C April   2018  – December 2020 DLPC3478

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  Internal Pullup and Pulldown Electrical Characteristics
    8. 6.8  DMD Sub-LVDS Interface Electrical Characteristics
    9. 6.9  DMD Low-Speed Interface Electrical Characteristics
    10. 6.10 System Oscillator Timing Requirements
    11. 6.11 Power Supply and Reset Timing Requirements
    12. 6.12 Parallel Interface Frame Timing Requirements
    13. 6.13 Parallel Interface General Timing Requirements
    14. 6.14 BT656 Interface General Timing Requirements
    15. 6.15 Flash Interface Timing Requirements
    16. 6.16 Other Timing Requirements
    17. 6.17 DMD Sub-LVDS Interface Switching Characteristics
    18. 6.18 DMD Parking Switching Characteristics
    19. 6.19 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Source
        1. 7.3.1.1 Supported Resolution and Frame Rates
        2. 7.3.1.2 3D Display
        3. 7.3.1.3 Parallel Interface
          1. 7.3.1.3.1 PDATA Bus – Parallel Interface Bit Mapping Modes
      2. 7.3.2  Pattern Display
        1. 7.3.2.1 External Pattern Mode
          1. 7.3.2.1.1 8-bit Monochrome Patterns
          2. 7.3.2.1.2 1-Bit Monochrome Patterns
        2. 7.3.2.2 Internal Pattern Mode
          1. 7.3.2.2.1 Free Running Mode
          2. 7.3.2.2.2 Trigger In Mode
      3. 7.3.3  Device Startup
      4. 7.3.4  SPI Flash
        1. 7.3.4.1 SPI Flash Interface
        2. 7.3.4.2 SPI Flash Programming
      5. 7.3.5  I2C Interface
      6. 7.3.6  Content Adaptive Illumination Control (CAIC)
      7. 7.3.7  Local Area Brightness Boost (LABB)
      8. 7.3.8  3D Glasses Operation
      9. 7.3.9  Test Point Support
      10. 7.3.10 DMD Interface
        1. 7.3.10.1 Sub-LVDS (HS) Interface
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Pattern projector for 3D depth scanning
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 3D Depth Scanner Using Internal Pattern Streaming Mode
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 PLL Design Considerations
    2. 9.2 System Power-Up and Power-Down Sequence
    3. 9.3 Power-Up Initialization Sequence
    4. 9.4 DMD Fast Park Control (PARKZ)
    5. 9.5 Hot Plug I/O Usage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PLL Power Layout
      2. 10.1.2 Reference Clock Layout
        1. 10.1.2.1 Recommended Crystal Oscillator Configuration
      3. 10.1.3 Unused Pins
      4. 10.1.4 DMD Control and Sub-LVDS Signals
      5. 10.1.5 Layer Changes
      6. 10.1.6 Stubs
      7. 10.1.7 Terminations
      8. 10.1.8 Routing Vias
      9. 10.1.9 Thermal Considerations
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 11.1.2 Device Nomenclature
        1. 11.1.2.1 Device Markings
      3. 11.1.3 Video Timing Parameter Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4 Revision History

Changes from Revision B (June 2019) to Revision C (December 2020)

  • 总数据表格式和订购更新Go
  • 删除了“（2D 和 3D）”Go
  • 将像素时钟更改为 155MHzGo
  • 更新了支持的 DMDGo
  • Reorganized Pin Function descriptionGo
  • Changed table "Pin Functions - Parallel Port Input" to match DLPC3430/35 Go
  • Changed table "Pin Functions - DMD Reset and Bias Control" to match DLPC3430/35 Go
  • Changed table "Pin Functions - DMD Sub-LVDS Interface" to match DLPC3430/35 Go
  • Changed table "Pin Functions - Peripheral Interface" to match DLPC3430/35 Go
  • Changed table "Pin Functions - GPIO Peripheral Interface" to match DLPC3430/35 Go
  • Changed description for GPIO_02 (removed option 2) Go
  • Changed description for GPIO_01 (removed option 2) Go
  • Deleted table "GPIO_01 and GPIO_02" Go
  • Changed table "Pin Functions - Clock and PLL Support" to match DLP3430/35 Go
  • Changed table "Pin Functions - Power and Ground" to match DLP3430/35 Go
  • Changed table "I/O Type Subscript Definition" to match DLP3430/35 Go
  • Updated Absolute Maximum Rating Go
  • Deleted row for VDDLP12 Go
  • Updated Recommended Operating ConditionsGo
  • Changed 1.00C to 0.1C (correction) Go
  • Updated Power Electrical Characteristics Go
  • Added table note "The reported numbers are valid only when operating the DLPC3478 in display mode."Go
  • Updated Pin Electrical CharacteristicsGo
  • Changed table "Internal Pullup and Pulldown Electrical Characteristics" to match DLP3430/35 Go
  • Updated DMD Sub-LVDS Interface Electrical Characteristics Go
  • Changed Images "Common Mode Voltage" and "Differential Output Signal" to match DLP3430/35 Go
  • Updated DMD Low-Speed Interface Electrical CharacteristicsGo
  • Changed Images "LS_CLK and LS_WDATA Slew Rate" and "DMD_DEN_ARSTZ Slew Rate" to match DLP3430/35 Go
  • Updated System Oscillator Timing RequirementsGo
  • Changed image "System Oscillators" to match DLP3430/35 Go
  • Updated Power Supply and Reset Timing Requirements Go
  • Changed image "Power_Up and Power-Down RESETZ Timing" to match DLP3430/35 Go
  • Changed table "Parallel Interface Frame Timing Requirements" to match DLP3430/35 Go
  • Changed image "Parallel Interface Frame Timing" to match DLP3430/35 Go
  • Changed table "Parallel Interface General Timing Requirements" to match DLP3430/35 Go
  • Changed image "Parallel Interface Pixel Timing" to match DLP3430/35 Go
  • Changed table "BT656 Interface General Timing Requirements" to match DLP3430/35 Go
  • Added BT.656 Interface Mode Bit Mapping Go
  • Deleted "with a programmable clock rate" Go
  • Changed 64Mb to 128Mb Go
  • Changed table "Flash Interface Timing Requirements" Go
  • Added Flash Interface Timing diagramGo
  • Updated maximum SPI flash size to 128MbGo
  • Added section "Other Timing Requirements" to match DLPC3430/35 Go
  • Added DMD Sub-LVDS Interface Switching CharacteristicsGo
  • Added DMD Parking Switching CharacteristicsGo
  • Added Chipset Component Usage Specification Go
  • Changed DLP2010 to DLP3010 Go
  • Added DLPA3005 Go
  • Changed DLP2010/DLP2010NIR (.2 WVGA) to DLP3010 (0.3 inch 720p) Go
  • Deleted section "Parameter Measurement Information" Go
  • Added subsection "Supported Resolution and Frame Rates"; includes table "Supported Input Source Ranges"Go
  • Changed 242 Hz to 122 Hz Go
  • Changed table notes in "Supported Resolution and Frame Rates"Go
  • Changed 854 x 480 to 1280 x 720 Go
  • Changed "Bits / Pixel" to "Bits per pixel" Go
  • Deleted "Fewer pins are used if multiple clocks are used per pixel transfer." Go
  • Changed title of subsection "Input Source - Frame Rates and 3-D Display Orientation" to "3-D Display"Go
  • Added DSI Interface - Supported Data Transfer Formats Go
  • Clarified that most video processing functions can be bypassed in pattern display mode Go
  • Changed description of TRIG_OUT_1 to indicate it's only active at the beginning of each input frame Go
  • Added Section 7.3.8 Go
  • Changed level of "DMD interface" (moved up) Go
  • Changed section "DMD Interface" to mach DLPC3430/35 Go
  • Changed "DLP2010 (.2 WVGA)" to "DLP3010 (0.3 inch 720p)" Go
  • Changed "four" to "two" Go
  • Changed DLP2010 to DLP3010 Go
  • Changed table "DLP2010 (.2 WVGA) DMD – Controller to 4-Lane DMD Pin Mapping Options" to "DLP3010 (0.3 inch 720p) DMD – ASIC to 8-Lane DMD Pin Mapping Options" (table copied from DLPS035)Go
  • Changed DLP2010 to DLP3010 Go
  • Updated external pattern streaming system block diagram.Go
  • Updated internal pattern streaming system block diagram.Go
  • Changed "is" to "can be" Go
  • Deleted " or DLP2010NIR" Go
  • Changed DLP2010 to DLP3010 Go
  • Deleted " or DLP2010NIR" Go
  • Changed DLP2010 to DLP3010 Go
  • Added section "Documentation Support" Go

Changes from Revision A (July 2018) to Revision B (June 2019)

  • 版本 C 更改替代了版本 B 更改Go

Changes from Revision * (April 2018) to Revision A (July 2018)

  • 首次公开发布完整数据表Go
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