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ZHCSIC5C June 2018 – August 2021 DLPC3479

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7.3.10.1 Sub-LVDS (HS) Interface

The DLPC3479 controller to DMD interface consists of a HS 1.8-V sub-LVDS output only interface with a maximum clock speed of 532-MHz DDR and a LS SDR (1.8-V LVCMOS) interface with a fixed clock speed of 120 MHz.Table 7-10 shows the two options available for the DLP4710 DMD.

Table 7-10 DLPC3479 (Primary and Secondary) to DLP4710LC (.47 1080p) DMD 8-Lane DMD Pin Mapping

DLPC3479 CONTROLLER 8 LANE DMD ROUTING OPTION #1
PRIMARY DLPC3479 PINS	SECONDARY DLPC3479 PINS	DMD PINS
HS_WDATA_D_P HS_WDATA_D_N	HS_WDATA_E_P HS_WDATA_E_N	Input DATA_p_0 Input DATA_n_0
HS_WDATA_C_P HS_WDATA_C_N	HS_WDATA_F_P HS_WDATA_F_N	Input DATA_p_1 Input DATA_n_1
HS_WDATA_B_P HS_WDATA_B_N	HS_WDATA_G_P HS_WDATA_G_N	Input DATA_p_2 Input DATA_n_2
HS_WDATA_A_P HS_WDATA_A_N	HS_WDATA_H_P HS_WDATA_H_N	Input DATA_p_3 Input DATA_n_3
HS_WDATA_H_P HS_WDATA_H_N	HS_WDATA_A_P HS_WDATA_A_N	Input DATA_p_4 Input DATA_n_4
HS_WDATA_G_P HS_WDATA_G_N	HS_WDATA_B_P HS_WDATA_B_N	Input DATA_p_5 Input DATA_n_5
HS_WDATA_F_P HS_WDATA_F_N	HS_WDATA_C_P HS_WDATA_C_N	Input DATA_p_6 Input DATA_n_6
HS_WDATA_E_P HS_WDATA_E_N	HS_WDATA_D_P HS_WDATA_D_N	Input DATA_p_7 Input DATA_n_7
DLPC3479 CONTROLLER 8 LANE DMD ROUTING OPTION #2
PRIMARY DLPC3479 PINS	SECONDARY DLPC3479 PINS	DMD PINS
HS_WDATA_E_P HS_WDATA_E_N	HS_WDATA_D_P HS_WDATA_D_N	Input DATA_p_0 Input DATA_n_0
HS_WDATA_F_P HS_WDATA_F_N	HS_WDATA_C_P HS_WDATA_C_N	Input DATA_p_1 Input DATA_n_1
HS_WDATA_G_P HS_WDATA_G_N	HS_WDATA_B_P HS_WDATA_B_N	Input DATA_p_2 Input DATA_n_2
HS_WDATA_H_P HS_WDATA_H_N	HS_WDATA_A_P HS_WDATA_A_N	Input DATA_p_3 Input DATA_n_3
HS_WDATA_A_P HS_WDATA_A_N	HS_WDATA_H_P HS_WDATA_H_N	Input DATA_p_4 Input DATA_n_4
HS_WDATA_B_P HS_WDATA_B_N	HS_WDATA_G_P HS_WDATA_G_N	Input DATA_p_5 Input DATA_n_5
HS_WDATA_C_P HS_WDATA_C_N	HS_WDATA_F_P HS_WDATA_F_N	Input DATA_p_6 Input DATA_n_6
HS_WDATA_D_P HS_WDATA_D_N	HS_WDATA_E_P HS_WDATA_E_N	Input DATA_p_7 Input DATA_n_7

Figure 7-23 DLP4710LC (.47 1080p) DMD Interface

The sub-LVDS high-speed interface waveform quality and timing on the DLPC34xx controller depends on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.

In an attempt to minimize the signal integrity analysis that would otherwise be required, the DMD Control and Sub-LVDS Signals layout section is provided as a reference of an interconnect system that satisfy both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB signal integrity). Variation from these recommendations may also work, but should be confirmed with PCB signal integrity analysis or lab measurements.