米6体育平台手机版

ZHCSO16A December 2021 – February 2023 DLPC4430

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机械数据 (封装 | 引脚)

ZPC|516
- MPBGAJ0

散热焊盘机械数据 (封装 | 引脚)

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zhcso16a_oa

6.11 DMD LVDS Interface Timing Requirements

		FROM (INPUT)	TO (OUTPUT)	MIN	MAX	UNIT
f_clock	Clock frequency, DCK_A	N/A	DCK_A	100	400	MHz
t_C	Cycle time, DCK_A⁽¹⁾	N/A	DCK_A	2475.3		ps
t_W(H)	Pulse duration, high	N/A	DCK_A	1093		ps
t_W(L)	Pulse duration, low	N/A	DCK_A	1093		ps
t_t	Transition time, t_t= t_f/t_r	N/A	DCK_A	100	400	ps
t_osu	Output Setup time at max clock rate⁽⁴⁾	DCK_A↑↓	SCA, DDA(15:0)	438		ps
t_oh	Output hold time at max clock rate⁽⁴⁾	DCK_A↑↓	SCA, DDA(15:0)	438		ps
f_clock	Clock frequency, DCK_B	N/A	DCK_B	100	400	MHz
t_C	Cycle time, DCK_B⁽¹⁾	N/A	DCK_B	2475.3		ps
t_W(H)	Pulse duration, high	N/A	DCK_B	1093		ps
t_W(L)	Pulse duration, low	N/A	DCK_B	1093		ps
t_t	Transition time, t_t= t_f/t_r	N/A	DCK_B	100	400	ps
t_osu	Output Setup time at max clock rate⁽⁴⁾	DCK_B↑↓	SCA, DDB(15:0)	438		ps
t_oh	Output hold time at max clock rate⁽⁴⁾	DCK_B↑↓	SCA, DDB(15:0)	438		ps
t_sk	Output Skew, Channel A to Channel B	DCK_A↑	DCK_B↑		250	ps

(1) The minimum cycle time (t_c) for DCK_A and DCL_B includes 1.0% spread spectrum modulation. User must verify that DMD can support this rate.

(4) Output Setup and Hold times for DMD clock frequencies below the maximum can be calculated as follows: t_osu(fclock) = t_osu(fmax) + 250000 × (1/fclock – 1/400) and t_oh(fclock) = t_oh(fmax) + 250000 × (1/fclock – 1/400) where fclock is in MHz.