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ZHCSC08C December 2013 – August 2015 DLPC6401

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9 Power Supply Recommendations

9.1 System Power Regulation

Table 10 shows the recommended power delivery budget for DC offset and AC noise as observed at the corresponding DLPC6401 power pins.

Table 10. Recommended Power Delivery Budget for DC Offset and AC Noise

ASIC POWER RAIL	USAGE	NOMINAL VOLTAGE	TOTAL SUPPLY MARGIN ⁽¹⁾
VDDC	ASIC core	1.2 V	±5%
VDD12_PLLM/ VDD12_PLLD	Internal PLLs	1.2 V	±5%
VDD_18_PLLM/ VDD18_PLLD	Internal PLLs	1.8 V	±5%⁽²⁾
VDD_DMD	DMD LPDDR I/O	1.9 V	±5%
VDD33	LVCMOS I/O	3.3 V	±5%
VDD12_FPD	FPD-Link LVDS I/F	1.2 V	±5%
VDD33_FPD	FPD-Link LVDS I/F	3.3 V	±5%

(1) Total supply margin = DC offset budget + AC noise budget

(2) When possible, TI suggests that a tighter supply tolerance (±3%) be used for the 1.8-V power to the PLLs to improve system noise immunity

TI strongly recommends that the VDD_18_PLLM and VDD_18_PLLD power feeding internal PLLs be derived from an isolated linear regulator to minimize the AC noise component. It is acceptable for VDD12_PLLM and VDD12_PLLD to be derived from the same regulator as the core VDD12, but they should be filtered.

9.2 System Power-Up Sequence

Although the DLPC6401 device requires an array of power supply voltages (1.2 V, 1.8 V, 1.9 V, and 3.3 V), there are no restrictions regarding the relative order of power supply sequencing. This is true for both power-up and power-down scenarios. Similarly, there is no minimum time between powering-up and powering-down the different supplies feeding the DLPC6401 device. However, note that it is not uncommon for there to be power-sequencing requirements for the devices that share the supplies with the DLPC6401 device. For example:

1.2-V core power should be applied whenever any I/O power is applied. This ensures the state of the associated I/O that are powered are controlled to a known state. Thus, TI recommends to apply core power first. Other supplies should be applied only after the 1.2-V ASIC core has ramped up.
All ASIC power should be applied before POSENSE is asserted to ensure proper power-up initialization is performed. 1.8-V PLL power, 1.9-V I/O power, and 3.3-V I/O power should remain applied as long as 1.2-V core power is applied and POSENSE is asserted.

It is assumed that all DLPC6401 device power-up sequencing is handled by external hardware. It is also assumed that an external power monitor will hold the DLPC6401 device in system reset during power-up (that is, POSENSE = 0). It should continue to assert system reset until all ASIC voltages have reached minimum specified voltage levels. During this time, all ASIC I/O are either tri-stated or driven low. The master PLL (PLLM) is released from reset upon the low-to-high transition of POSENSE, but the DLPC6401 device keeps the rest of the ASIC in reset for an additional 100 ms to allow the PLL to lock and stabilize its outputs. After this 100-ms delay, ARM9-related internal resets are de-asserted, causing the microprocessor to begin its boot-up routine.

Figure 16 shows the recommended DLPC6401 system power-up sequence.

Figure 16. System Power-Up Sequence

9.3 Power-On Sense (POSENSE) Support

It is difficult to set up a power monitor to trip exactly on the ASIC minimum supply voltage specification. Thus for practical reasons, TI recommends that the external power monitor generating POSENSE target its threshold to 90% of the minimum supply voltage specifications and ensure that POSENSE remain low a sufficient amount of time for all supply voltages to reach minimum ASIC requirements and stabilize. Note that the trip voltage for detecting the loss of power is not critical for POSENSE and thus may be as low as 50% of rated supply voltages. In addition, the reaction time to respond to a low voltage condition is not critical for POSENSE; however, PWRGOOD does have much more critical requirements in these areas.

9.4 System Environment and Defaults

9.4.1 DLPC6401 System Power-Up and Reset Default Conditions

Following system power-up, the DLPC6401 device performs a power-up initialization routine that defaults the ASIC to its normal power mode, in which ARM9-related clocks are enabled at their full rate and associated resets are released. Most other clocks default to disabled state with associated resets asserted until released by the processor. These same defaults are also applied as part of all system reset events (watch dog timer timeout, and so on) that occur without removing or cycling power.

Following power-up or system reset initialization, the ARM9 boots from an external flash memory after which it enables the rest of the ASIC clocks. When system initialization is complete, application software determines if and when to enter low-power mode.

9.4.2 1.2-V System Power

The DLPC6401 device can support a power delivery system with a single 1.2-V power source derived from a switching regulator. The DLPC6401 main core should receive 1.2-V power directly from the regulator output and the internal ASIC PLLs (VDDC, VDD12_PLLD, and VDD12_PLLM) should receive individually-filtered versions of this 1.2-V power. For specific filter recommendations, see PCB Layout Guidelines for Internal ASIC Power.

9.4.3 1.8-V System Power

A single 1.8-V power source should be used to supply both DLPC6401 internal PLLs. To keep this power as clean as possible, TI recommends that this power be sourced by a linear regulator that is individually filtered for each PLL (VDD_18_PLLD and VDD_18PLLM). For specific filter recommendations, see PCB Layout Guidelines for Internal ASIC Power.

9.4.4 1.9-V System Power

To maximize signal integrity, TI recommends to use an independent linear regulator to source the 1.9-V supply that supports the DMD interface (VDD_DMD). To achieve maximum performance, this supply must be tightly regulated to operating within a 1.9-V ±0.1 V range.

9.4.5 3.3-V System Power

The DLPC6401 device can support a power delivery system with a single 3.3-V power sources derived from a switching regulator. This 3.3-V power supplies all of the LVCMOS I/O. 3.3-V power should remain active in all power modes (VDD33) for which 1.2-V core power is applied.

9.4.6 FPD-Link Input LVDS System Power

The DLPC6401 device supports an FPD-Link compatible, LVDS input for an additional method of inputting video or graphics data for display. This interface has some special ASIC power considerations that are separate from the other ASIC 1.2- or 3.3-V power rails. Figure 17 shows a FPD-Link 1.2-V power pin (VDD12_FPD) configuration example.

Figure 17. FPD-Link

In addition, TI recommends to place 0.1-µF low equivalent series resistor (ESR) capacitors to ground as close to the FPD-Link lower pins of the ASIC as possible. FPD-Link 3.3-V power pins (FPD33) should also use external capacitors in the same manner as for VDD12_FPD pins.

When FPD-Link is not used, the user can omit the previously mentioned filtering. However, the corresponding voltages must still be provided to avoid potential long-term reliability issues.

9.4.7 Power Good (PWRGOOD) Support

The PWRGOOD signal is defined as an early warning signal that alerts the ASIC 500 µs before DC supply voltages drop below specifications. This allows the ASIC to park the DMD ensuring the integrity of future operation. For practical reasons, TI recommends that the monitor sensing PWRGOOD be on the input side of supply regulators.

9.4.8 5-V Tolerant Support

The DLPC6401 device does not support any 5-V tolerant I/O. However, note that source signals ALF_HSYNC, ALF_VSYNC, and I²C typically have 5-V requirements and special measures must be taken to support them. TI recommends the use of a 5- to 3.3-V level shifter.