ZHCSC08C December   2013  – August 2015 DLPC6401

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Electrical Characteristics (Normal Mode)
    7. 6.7  System Oscillators Timing Requirements
    8. 6.8  Test and Reset Timing Requirements
    9. 6.9  JTAG Interface: I/O Boundary Scan Application Timing Requirements
    10. 6.10 Port 1 Input Pixel Interface Timing Requirements
    11. 6.11 Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing Requirements
    12. 6.12 Synchronous Serial Port (SSP) Interface Timing Requirements
    13. 6.13 Programmable Output Clocks Switching Characteristics
    14. 6.14 Synchronous Serial Port (SSP) Interface Switching Characteristics
    15. 6.15 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 System Reset Operation
        1. 7.3.1.1 Power-Up Reset Operation
        2. 7.3.1.2 System Reset Operation
        3. 7.3.1.3 Spread Spectrum Clock Generator Support
        4. 7.3.1.4 GPIO Interface
        5. 7.3.1.5 Source Input Blanking
        6. 7.3.1.6 Video and Graphics Processing Delay
      2. 7.3.2 Program Memory Flash/SRAM Interface
        1. 7.3.2.1 Calibration and Debug Support
        2. 7.3.2.2 Board-Level Test Support
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Recommended MOSC Crystal Oscillator Configuration
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
    1. 9.1 System Power Regulation
    2. 9.2 System Power-Up Sequence
    3. 9.3 Power-On Sense (POSENSE) Support
    4. 9.4 System Environment and Defaults
      1. 9.4.1 DLPC6401 System Power-Up and Reset Default Conditions
      2. 9.4.2 1.2-V System Power
      3. 9.4.3 1.8-V System Power
      4. 9.4.4 1.9-V System Power
      5. 9.4.5 3.3-V System Power
      6. 9.4.6 FPD-Link Input LVDS System Power
      7. 9.4.7 Power Good (PWRGOOD) Support
      8. 9.4.8 5-V Tolerant Support
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PCB Layout Guidelines for Internal ASIC Power
      2. 10.1.2 PCB Layout Guidelines for Quality Auto-Lock Performance
      3. 10.1.3 DMD Interface Considerations
      4. 10.1.4 General Handling Guidelines for Unused CMOS-Type Pins
    2. 10.2 Layout Example
    3. 10.3 Thermal Considerations
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 器件命名规则
        1. 11.1.1.1 视频时序参数定义
        2. 11.1.1.2 器件标记
    2. 11.2 社区资源
    3. 11.3 商标
    4. 11.4 静电放电警告
    5. 11.5 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

5 Pin Configuration and Functions

ZFF PACKAGE
419-PIN BGA
TOP VIEW
DLPC6401 PO_DLPS031.gif

Pin Functions

PIN(1) I/O (2) INTERNAL TERMINATION CLK SYSTEM DESCRIPTION
NAME NO. POWER TYPE
CONTROL
EXT_ARST H20 VDD33 O1 Async External reset output, LOW true. This output is asserted low immediately upon asserting power-up reset (POSENSE) low and remains low while POSENSE remains low. EXT_ARSTZ continues to be held low after the release of power-up reset (that is, POSENSE set high) until released by software. EXT_ARSTZ is also asserted low approximately 5 µs after the detection of a PWRGOOD or any internally-generated reset. In all cases, it remains active for a minimum of 2 ms after the reset condition is released by software. Note, the ASIC contains a software register that can be used to independently drive this output.
PWRGOOD H19 VDDC I4
H		 Async Power Good is an active-high signal with hysteresis that is generated by an external power supply or voltage monitor. A high value indicates all power is within operating voltage specifications and the system is safe to exit its reset state. A transition from high to low should indicate that the controller or DMD supply voltage will drop below their rated minimum level within the next 0.5 ms (POSENSE must remain active high during this interval). This is an early warning of an imminent power loss condition. This warning is required to enhance long-term DMD reliability. A DMD park sequence, followed by a full controller reset, is performed by the DLPC6401 when PWRGOOD goes low for a minimum of 4 µs protecting the DMD. This minimum de-assertion time is used to protect the input from glitches. Following this, the DLPC6401 is held in its reset state as long as PWRGOOD is low. PWRGOOD must be driven high for typical operation. The DLPC6401 device acknowledges PWRGOOD as active after it is driven high for a minimum of 625 ns. Uses hysteresis.
POSENSE G21 I4
H		 Async Power-On Sense is an active-high input signal with hysteresis that is generated by an external voltage monitor circuit. POSENSE must be driven inactive (low) when any of the controller supply voltages are below minimum operating voltage specifications. POSENSE must be active (high) when all controller supply voltages remain above minimum specifications.
POWER_ON_OFF N21 VDD33 B2 Async Power On or Power Off is an active-high signal that indicates the power of the system. Power On or Power Off is high when the system is in power-up state, and low when the system is in standby. Power On or Power Off can also be used to power on or off an external power supply.
INIT_DONE F19 VDD33 B2 Async Prior to transferring part of code from parallel flash content to internal memory, the internal memory is initialized and a memory test is performed. The result of this test (pass or fail) is recorded in the system status. If memory test fails, the initialization process is halted. INIT_DONE is asserted twice to indicate an error situation. See Figure 12.
I2C_ADDR_SEL F21 VDD33 B2 Async This signal is sampled during power-up. If the signal is low, the I2C addresses are 0x34 and 0x35. If the signal is low, the I2C are 0x3A and 0x3B.
I2C1_SCL J3 VDD33 B2 Requires an external pullup to 3.3 V. The minimum acceptable pullup value is
1 kΩ.		 N/A I2C clock. Bidirectional, open-drain signal. I2C slave clock input from the external processor. This bus supports 400 kHz.
I2C1_SDA J4 VDD33 B2 Requires an external pullup to 3.3 V. The minimum acceptable pullup value is
1 kΩ.		 I2C1_SCL I2C data. Bidirectional, open-drain signal. I2C slave to accept command or transfer data to and from the external processor. This bus supports 400 kHz.
I2C0_SCL M2 VDD33 B8 Requires an external pullup to 3.3 V. The minimum acceptable pullup value is 1 kΩ. This input is not
5-V tolerant.		 N/A I2C bus 0, clock; I2C master for on-board peripherals such as temperature sensor. This bus supports 400-kHz, fast-mode operation.
I2C0_SDA M3 VDD33 B8 Requires an external pullup to 3.3 V. The minimum acceptable pullup value is 1 kΩ. This input is not
5-V tolerant.		 I2C0_SCL I2C bus 0, data; I2C master for on-board peripherals such as temperature sensor. This bus supports 400-kHz, fast-mode operation.
SYSTEM CLOCK
MOSC A14 VDD33 I10 N/A System clock oscillator input (3.3-V LVCMOS). Note that the MOSC must be stable a maximum of 25 ms after POSENSE transitions from high to low.
MOSCN A15 VDD33 O10 N/A MOSC crystal return
PORT 1: PARALLEL VIDEO AND GRAPHICS INPUT(3)(4)(5)
P1A_CLK W15 VDD33 I4 Includes an internal pulldown N/A Port 1 input data pixel write clock 'A'
P1B_CLK AB17 VDD33 I4 Includes an internal pulldown N/A Port 1 input data pixel write clock 'B'
P1C_CLK Y16 VDD33 I4 Includes an internal pulldown N/A Port 1 input data pixel write clock 'C'
P1_VSYNC Y15 VDD33 B1
H		 Includes an internal pulldown P1A_CLK Port 1 vertical sync. Uses hysteresis
P1_HSYNC AB16 VDD33 B1
H		 Includes an internal pulldown P1A_CLK Port 1 horizontal sync. Uses hysteresis
P1_DATEN AA16 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 data enable
P1_FIELD W14 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 field sync. Required for interlaced sources only (and not progressive)
P1_A_9 AB20 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 A channel input pixel data (bit weight 128)
P1_A_8 AA19 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 A channel input pixel data (bit weight 64)
P1_A_7 Y18 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 A channel input pixel data (bit weight 32)
P1_A_6 W17 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 A channel input pixel data (bit weight 16)
P1_A_5 AB19 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 A channel input pixel data (bit weight 8)
P1_A_4 AA18 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 A channel input pixel data (bit weight 4)
P1_A_3 Y17 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 A channel input pixel data (bit weight 2)
P1_A_2 AB18 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 A channel input pixel data (bit weight 1)
P1_A_1 W16 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 A channel input pixel data (bit weight 0.5)
P1_A_0 AA17 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 A channel input pixel data (bit weight 0.25)
P1_B_9 U21 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 B channel input pixel data (bit weight 128)
P1_B_8 U20 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 B channel input pixel data (bit weight 64)
P1_B_7 V22 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 B channel input pixel data (bit weight 32)
P1_B_6 U19 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 B channel input pixel data (bit weight 16)
P1_B_5 V21 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 B channel input pixel data (bit weight 8)
P1_B_4 W22 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 B channel input pixel data (bit weight 4)
P1_B_3 W21 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 B channel input pixel data (bit weight 2)
P1_B_2 AA20 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 B channel input pixel data (bit weight 1)
P1_B_1 Y19 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 B channel input pixel data (bit weight 0.5)
P1_B_0 W18 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 B channel input pixel data (bit weight 0.25)
P1_C_9 P21 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 C channel input pixel data (bit weight 128)
P1_C_8 P22 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 C channel input pixel data (bit weight 64)
P1_C_7 R19 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 C channel input pixel data (bit weight 32)
P1_C_6 R20 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 C channel input pixel data (bit weight 16)
P1_C_5 R21 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 C channel input pixel data (bit weight 8)
P1_C_4 R22 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 C channel input pixel data (bit weight 4)
P1_C_3 T21 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 C channel input pixel data (bit weight 2)
P1_C_2 T20 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 C channel input pixel data (bit weight 1)
P1_C_1 T19 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 C channel input pixel data (bit weight 0.5)
P1_C_0 U22 VDD33 I4 Includes an internal pulldown P1A_CLK Port 1 C channel input pixel data (bit weight 0.25)
PORT 2: FPD-LINK COMPATIBLE VIDEO AND GRAPHICS INPUT(6)
RCK_IN_P Y9 VDD33_FPD I5 Includes weak internal pulldown N/A Positive differential input signal for clock, FPD-Link receiver
RCK_IN_N W9 VDD33_FPD I5 Includes weak internal pulldown N/A Negative differential input signal for clock, FPD-Link receiver
RA_IN_P AB10 VDD33_FPD I5 Includes weak internal pulldown RCK_IN Positive differential input signal for data channel A, FPD-Link receiver
RA_IN_N AA10 VDD33_FPD I5 Includes weak internal pulldown RCK_IN Negative differential input signal for data channel A, FPD-Link receiver
RB_IN_P Y11 VDD33_FPD I5 Includes weak internal pulldown RCK_IN Positive differential input signal for data channel B, FPD-Link receiver
RB_IN_N W11 VDD33_FPD I5 Includes weak internal pulldown RCK_IN Negative differential input signal for data channel B, FPD-Link receiver
RC_IN_P AB12 VDD33_FPD I5 Includes weak internal pulldown RCK_IN Positive differential input signal for data channel C, FPD-Link receiver
RC_IN_N AA12 VDD33_FPD I5 Includes weak internal pulldown RCK_IN Negative differential input signal for data channel C, FPD-Link receiver
RD_IN_P Y13 VDD33_FPD I5 Includes weak internal pulldown RCK_IN Positive differential input signal for data channel D, FPD-Link receiver
RD_IN_N W13 VDD33_FPD I5 Includes weak internal pulldown RCK_IN Negative differential input signal for data channel D, FPD-Link receiver
RE_IN_P AB14 VDD33_FPD I5 Includes weak internal pulldown RCK_IN Positive differential input signal for data channel E, FPD-Link receiver
RE_IN_N AA14 VDD33_FPD I5 Includes weak internal pulldown RCK_IN Negative differential input signal for data channel E, FPD-Link receiver
DMD INTERFACE
DMD_D0 A8
DMD_D1 B8
DMD_D2 C8
DMD_D3 D8
DMD_D4 B11
DMD_D5 C11
DMD_D6 D11
DMD_D7 E11
DMD_D8 C7
DMD_D9 B10
DMD_D10 E7
DMD_D11 D10 VDD_DMD O7 DMD_DCLK DMD data pins. DMD data pins are DDR signals that are clocked on both edges of DMD_DCLK.
All 24 DMD data signals are use to interface to the DLP4500.
DMD_D12 A6
DMD_D13 A12
DMD_D14 B12
DMD_D15 C12
DMD_D16 D12
DMD_D17 B7
DMD_D18 A10
DMD_D19 D7
DMD_D20 B6
DMD_D21 E9
DMD_D22 C10
DMD_D23 C6
DMD_DCLK A9 VDD_DMD O7 N/A DMD data clock (DDR)
DMD_LOADB B9 VDD_DMD O7 DMD_DCLK DMD data load signal (active-low)
DMD_SCTRL C9 VDD_DMD O7 DMD_DCLK DMD data serial control signal
DMD_TRC D9 VDD_DMD O7 DMD_DCLK DMD data toggle rate control
DMD_DRC_BUS D5 VDD_DMD O7 DMD_SAC_CLK DMD reset control bus data
DMD_DRC_STRB C5 VDD_DMD O7 DMD_SAC_CLK DMD reset control bus strobe
DMD_DRC_OE B5 VDD_DMD O7 Requires a 30 to 51-kΩ external pullup resistor to VDD_DMD. Async DMD reset control enable (active low)
DMD_SAC_BUS D6 VDD_DMD O7 DMD_SAC_CLK DMD stepped-address control bus data
DMD_SAC_CLK A5 VDD_DMD O7 N/A DMD stepped-address control bus clock
DMD_PWR_EN G20 VDD_DMD O2 Async DMD Power Enable control. This signal indicates to an external regulator that the DMD is powered.
EXRES A3 O Async DMD drive strength adjustment precision reference. A ±1% external precision resistor should be connected to this pin.
FLASH INTERFACE
PM_CS_0 U3 VDD33 O2 Async Reserved for future use. On the PCB, connect to VDD33 through a pullup resistor.
PM_CS_1 U2 VDD33 O2 Async Boot flash (active low). Required for boot memory
PM_CS_2 U1 VDD33 O2 Async Reserved for future use. On the PCB, connect to VDD33 through a pullup resistor.
PM_ADDR_22 V3 B2
PM_ADDR_21 W1
PM_ADDR_20 W2
PM_ADDR_19 Y1
PM_ADDR_18 AB2
PM_ADDR_17 AA3
PM_ADDR_16 Y4
PM_ADDR_15 W5
PM_ADDR_14 AB3
PM_ADDR_13 AA4
PM_ADDR_12 Y5
PM_ADDR_11 W6 VDD33 O2 Async Flash memory address bit
PM_ADDR_10 AB4
PM_ADDR_9 AA5
PM_ADDR_8 Y6
PM_ADDR_7 W7
PM_ADDR_6 AB5
PM_ADDR_5 AA6
PM_ADDR_4 Y7
PM_ADDR_3 AB6
PM_ADDR_2 W8
PM_ADDR_1 AA7
PM_ADDR_0 AB7
PM_WE V2 VDD33 O2 Async Write enable (active low)
PM_OE U4 VDD33 O2 Async Output enable (active low)
PM_BLS_1 AA8 VDD33 O2 Async Upper byte(15:8) enable
PM_BLS_0 AB8 VDD33 O2 Async Lower byte(7:0) enable
PM_DATA_15 M1
PM_DATA_14 N1
PM_DATA_13 N2
PM_DATA_12 N3 VDD33 B2 Async Data bits, upper byte
PM_DATA_11 N4
PM_DATA_10 P1
PM_DATA_9 P2
PM_DATA_8 P3
PM_DATA_7 P4
PM_DATA_6 R2
PM_DATA_5 R3
PM_DATA_4 R4 VDD33 B2 Async Data bits, lower byte
PM_DATA_3 T1
PM_DATA_2 T2
PM_DATA_1 T3
PM_DATA_0 T4
LED DRIVER INTERFACE
LEDR_PWM K2 LED red PWM output enable control
LEDG_PWM K3 VDD33 O2 Async LED green PWM output enable control
LEDB_PWM K4 LED blue PWM output enable control
LEDR_EN L3 LED red PWM output
LEDG_EN L4 VDD33 O2 Async LED green PWM output
LEDB_EN K1 LED blue PWM output
PERIPHERAL INTERFACE
UART_TXD L19 VDD33 O2 Async Transmit data output. Reserved for debug messages
UART_RXD L21 VDD33 I4 Async Receive data input. Reserved for debug messages
UART_RTS M19 VDD33 O2 Async Ready to send hardware flow control output. Reserved for debug messages
UART_CTS L20 VDD33 I4 Async Clear to send hardware flow control input. Reserved for debug messages
GENERAL PURPOSE I/O (GPIO)(7)
GPIO_37 K21 VDD33 B2 Async None
GPIO_36 G1 VDD33 B2 Async None
GPIO_35 H4 VDD33 B2 Async None
GPIO_34 H3 VDD33 B2 Async None
GPIO_33 H2 VDD33 B2 Async None
GPIO_32 F22 VDD33 B2 Async None
GPIO_31 G19 VDD33 B2 Async None
GPIO_29 F20 VDD33 B2 Async None
GPIO_28 E22 VDD33 B2 Async None
GPIO_27 E21 VDD33 B2 Async None
GPIO_25 D22 VDD33 B2 Async None
GPIO_24 E20 VDD33 B2 Async None
GPIO_23 D21 VDD33 B2 Async None
GPIO_21 N20 VDD33 B2 Async None
GPIO_20 N19 VDD33 B2 Async None
GPIO_19 D18 VDD33 B2 Async None
GPIO_18 C18 VDD33 B2 Async None
GPIO_15 B19 VDD33 B2 Async None
GPIO_14 B18 VDD33 B2 Async None
GPIO_13 L2 VDD33 B2 Async None
GPIO_12 M4 VDD33 B2 Async None
GPIO_11 A19 VDD33 B2 Async None
GPIO_10 C17 VDD33 B2 Async None
GPIO_06 A18 VDD33 B2 Async None
GPIO_05 D16 VDD33 B2 Async None
GPIO_04 C16 VDD33 B2 Async None
GPIO_03 B16 VDD33 B2 Async None
GPIO_02 A17 VDD33 B2 Async None
GPIO_00 C15 VDD33 B2 Async None
OTHER INTERFACES
FAN_LOCKED B17 VDD33 B2 Async Feedback from fan to indicate fan is connected and running
FAN_PWM D15 VDD33 B2 Async Fan PWM speed control
BOARD LEVEL TEST AND DEBUG
TDI P18 VDD33 I4 Includes internal pullup TCK JTAG serial data in(8)
TCK R18 VDD33 I4 Includes internal pullup N/A JTAG serial data clock(8)
TMS1 V15 VDD33 I4 Includes internal pullup TCK JTAG test mode select(8)
TDO1 L18 VDD33 O1 TCK JTAG serial data out(8)
TRST V17 VDD33 I4
H		 Includes internal pullup Async JTAG, RESET (active low). This pin should be pulled high (or left unconnected) when the JTAG interface is in use for boundary scan. Connect this pin to ground otherwise. Failure to tie this pin low during normal operation causes startup and initialization problems.(8)
RTCK G18 VDD33 O2 N/A JTAG return clock(1)
ICTSEN V6 VDD33 I4
H		 Includes internal pull down. External pulldown recommended for added protection. Async IC Tri-State Enable (active high). Asserting high tri-states all outputs except the JTAG interface.
(1) For instructions on handling unused pins, see General Handling Guidelines for Unused CMOS-Type Pins.
(2) I/O Type: I = Input, O = Output, B = Bidirectional, and H = Hysteresis. See Table 1 for subscript explanation.
(3) Port 1 can be used to support multiple source options for a given product (that is, HDMI, BT656). To do so, the data bus from both source components must be connected to the same port 1 pins and control given to the DLPC6401 to tri-state the inactive source. Tying them together like this causes some signal degradation due to reflections on the tri-stated path.
(4) The A, B, and C input data channels of port 1 can be internally swapped for optimum board layout.
(5) Sources feeding less than the full 10-bits per color component channel should be MSB justified when connected to the DLPC6401 and LSBs tied off to 0. For example, an 8-bit per color input should be connected to bits 9:2 of the corresponding A, B, or C input channel. BT656 are 8 or 10 bits in width. If a BT656-type input is used, the data bits must be MSB justified as with the other types of input sources on either of the A, B, or C data input channels.
(6) Port 2 is a single-channel FPD-Link compatible input interface. FPD-Link is a defacto industry standard FPD interface, which uses the high-bandwidth capabilities of LVDS signaling to serialize video and graphics data down to a couple wires to provide a low-wire count and low-EMI interface. Port 2 supports source rates up to a maximum effective clock of 90 MHz. The port 2 input pixel data must adhere to one of four supported data mapping formats (see Table 2). Given that port 2 inputs contain weak pulldown resistors, they can be left floating when not used.
(7) GPIO signals must be configured by software for input, output, bidirectional, or open-drain. Some GPIOs have one or more alternate use modes, which are also software configurable. The reset default for all optional GPIOs is as an input signal. However, any alternate function connected to these GPIO pins with the exception of general-purpose clocks and PWM generation, are reset. An external pullup to the 3.3-V supply is required for each signal configured as open-drain. External pullup or pulldown resistors may be required to ensure stable operation before software is able to configure these ports.
(8) All JTAG signals are LVCMOS-compatible.

Functional Pin Descriptions (Reserved Pins)

PIN(1) I/O (2) INTERNAL TERMINATION CLK SYSTEM DESCRIPTION
NAME NO. POWER TYPE
RESERVED V7 VDD33 I4
H		 Includes internal pulldown N/A Connect directly to ground on the PCB.
RESERVED N22, M22, P19, P20 VDD33 I4 Includes an internal pulldown N/A Reserved(1)
RESERVED V16 VDD33 I4 Includes an internal pullup N/A
RESERVED D1, J2 VDD33 I4 N/A
RESERVED F1, F2, G2, G3, G4 VDD33 O2 Includes internal pulldown N/A Leave these pins unconnected(1)
RESERVED F3, J1, M21 VDD33 O2 N/A
RESERVED H20, M18, M20 VDD33 O1 N/A
RESERVED H21, H22, J19, J20, J21, J22, K19, K20 VDD33 B2 Includes internal pulldown N/A Reserved(1)
RESERVED C1, D2, F4 VDD33 B2 N/A
RESERVED E3, E2 VDD33 — Async Reserved
(1) For instructions on handling unused pins, see General Handling Guidelines for Unused CMOS-Type Pins.
(2) I/O Type: I indicates input, O indicates output, B indicates bidirectional, and H indicates hysteresis. See Table 1 for subscript explanation.

Table 1. I/O Type Subscript Definition

I/O ESD STRUCTURE
SUBSCRIPT DESCRIPTION
1 3.3-V LVCMOS I/O buffer, with 4-mA drive ESD diode to VDD33 and GND
2 3.3-V LVCMOS I/O buffer, with 8-mA drive ESD diode to VDD33 and GND
3 3.3-V LVCMOS I/O buffer, with 12-mA drive ESD diode to VDD33 and GND
4 3.3-V LVCMOS receiver ESD diode to VDD33 and GND
5 3.3-V LVDS receiver (FPD-Link I/F) ESD diode to VDD33 and GND
6 None N/A
7 1.9-V LPDDR output buffer (DMD I/F) ESD diode to VDD_DMD and GND
8 3.3-V I2C with 12-mA sink ESD diode to VDD33 and GND
10 OSC 3.3-V I/O compatible LVCMOS ESD diode to VDD33 and GND
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