米6体育平台手机版

ZHCSC08C December 2013 – August 2015 DLPC6401

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

ZFF|419
- MPBGAF9

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zhcsc08c_oa

6 Specifications

6.1 Absolute Maximum Ratings

over recommended operating free-air temperature (unless otherwise noted) ⁽¹⁾

			MIN	MAX	UNIT
ELECTRICAL
	Supply voltage⁽²⁾	VDDC (core 1.2-V power)	–0.5	1.7	V
		VDD33 (CMOS I/O)	–0.5	3.8
		VDD_DMD (DMD driver power)	–0.5	2.3
		VDD12_FPD (FPD-Link LVDS interface 1.2-V power)	–0.5	1.7
		VDD33_FPD (FPD-Link LVDS interface 3.3-V power)	–0.5	3.8
		VDD12_PLLD (DDR clock generator – digital)	–0.5	1.7
		VDD12_PLLM (master clock generator – digital)	–0.5	1.7
		VDD_18_PLLD (DDR clock generator – analog)	–0.5	2.3
		VDD_18_PLLM (master clock generator – analog)	–0.5	2.3
V_I	Input voltage⁽³⁾	OSC (BC1850)	–0.3	3.6
		LVCMOS (BT3350)	–0.5	3.6
		I²C (BT3350)	–0.5	3.6
		LVDS (BT3350)	–0.5	3.6
V_O	Output voltage	DMD LPDDR (BC1850)	–0.3	2.0
		LVCMOS (BT3350)	–0.5	3.6
		I²C (BT3350)	–0.5	3.6
ENVIRONMENTAL
T_J	Operating junction temperature		0	115	°C
T_stg	Storage temperature		–40	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to GND.

(3) Applies to external input and bidirectional buffers.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
		Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500
		Machine model (MM)	±150

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		I/O⁽¹⁾	MIN	NOM	MAX	UNIT
VDD33	3.3-V supply voltage, I/O		3.135	3.3	3.465	V
VDD_DMD	1.9-V supply voltage, I/O		1.8	1.9	2	V
VDD_18_PLLD	1.8-V supply voltage, PLL analog		1.71	1.8	1.89	V
VDD_18_PLLM	1.8-V supply voltage, PLL analog		1.71	1.8	1.89	V
VDD12	1.2-V supply voltage, core logic		1.116	1.2	1.26	V
VDD12_PLLD	1.2-V supply voltage, PLL digital		1.116	1.2	1.26	V
VDD12_PLLM	1.2-V supply voltage, PLL digital		1.116	1.2	1.26	V
V_I	Input voltage	OSC (10)	0		VDD33	V
		3.3-V LVCMOS (1, 2, 3, 4)	0		VDD33
		3.3-V I²C (8)	0		VDD33
		3.3-V LVDS (5)	0.6		2.2
V_O	Output voltage	3.3-V LVCMOS (1, 2, 3, 4)	0		VDD33	V
		3.3-V I²C (8)	0		VDD33
		1.9-V LPDDR (7)	0		VDD_DMD
T_A	Operating ambient temperature range	See ⁽²⁾	0		55	°C
T_C	Operating top-center case temperature	See ⁽³⁾⁽⁴⁾	0		104	°C
T_J	Operating junction temperature		0		105	°C

(1) The number inside each parenthesis for the I/O refers to the type defined in the I/O type subscript definition section.

(2) Assumes a minimum 1-m/s airflow along with the JEDEC thermal resistance and associated conditions as listed www.ti.com/packaging. Thus, this is an approximate value that varies with environment and PCB design.

(3) Maximum thermal values assume maximum power of 3 W.

(4) Assume ψ_JT equals 0.33 C/W.

6.4 Thermal Information⁽¹⁾

THERMAL METRIC⁽¹⁾		DLPC6401	UNIT
		ZFF (BGA)
		419 PINS
ψ_JT	Junction-to-top characterization parameter	0.33	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application Report, SPRA953.

6.5 Electrical Characteristics⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	High-level input threshold voltage	OSC (10)		2			V
		3.3-V LVCMOS (1, 2, 3, 4)		2
		3.3-V I²C (8)		2.4
V_IL	Low-level input threshold voltage	OSC (10)				0.8	V
		3.3-V LVCMOS (1, 2, 3, 4)				0.8
		3.3-V I²C (8)				1
RI	Receiver input impedance	3.3-V LVDS (5)	VDDH = 3.3 V	90	110	132	Ω
Vidth	Input differential threshold	3.3-V LVDS (5)		–200		200	mV
\|Vid\|	Absolute input differential voltage	3.3-V LVDS (5)		200		600	mV
VICM	Input common mode voltage range	3.3-V LVDS (5)	At minimum absolute input differential voltage	0.7		2.1	V
VICM	Input common mode voltage range	3.3-V LVDS (5)	At max absolute input differential voltage	0.9		1.9	V
VHYS	Hysteresis (VT+ – VT–)	3.3-V LVCMOS (1, 2, 3, 4)			400		mV
VHYS	Hysteresis (VT+ – VT–)	3.3-V I²C (8)			550		mV
V_OH	High-level output voltage	3.3-V LVCMOS (1, 2, 3)	I_OH= Max rated	2.8			V
V_OH	High-level output voltage	1.9-V DMD LPDDR (7)	I_OH = –0.1 mA	0.9 × VDD_DMD			V
V_OL	Low-level output voltage	1.9-V DMD LPDDR (7)	I_OL = 0.1 mA			0.1 × VDD_DMD	V
		3.3-V LVCMOS (1, 2, 3)	I_OL = Max rated			0.4
		3.3-V I²C (8)	I_OL = 3-mA sink			0.4
I_IH	High-level input current	OSC (10)				10.0	µA
		3.3-V LVCMOS (1 to 4) (without internal pulldown)	V_IH = VDD33			10
		3.3 V LVCMOS (1 to 4) (with internal pulldown)	V_IH= VDD33			200
		3.3 V I²C (8)	V_IH = VDD33			10
I_IL	Low-level input current	OSC (10)				–10.0	µA
		3.3-V LVCMOS (1 to 4) (without internal pullup)	V_OH = VDD33			–10
		3.3-V LVCMOS (1 to 4) (with internal pullup)	V_OH= VDD33			–200
		3.3-V I²C (8)	V_OH = VDD33			–10
I_OH	High-level output current	1.9-V DMD LPDDR (7)	V_O = 1.5 V	–4			mA
		3.3-V LVCMOS (1)	V_O = 2.4 V	–4
		3.3-V LVCMOS (2)	V_O = 2.4 V	–8
		3.3-V LVCMOS (3)	V_O = 2.4 V	–12
I_OL	Low-level output current	1.9-V DMD LPDDR (7)	V_O = 0.4 V	4			mA
		3.3-V LVCMOS (1)	V_O = 0.4 V	4
		3.3-V LVCMOS (2)	V_O = 0.4 V	8
		3.3-V LVCMOS (3)	V_O = 0.4 V	12
		3.3-V I²C (8)		3
I_OZ	High-impedance leakage current	3.3-V LVCMOS (1, 2, 3)		–10		10	µA
I_OZ	High-impedance leakage current	3.3-V I²C (8)		–10		10	µA
C_I	Input capacitance (including package)	3.3-V LVCMOS (2)		2.8	3.3	4	pF
		3.3-V LVCMOS (4)		2.7	3.4	4.2
		3.3-V I²C (8)		3	3.2	3.5

(1) The number inside each parenthesis for the I/O refers to the type defined in Table 1.

6.6 Electrical Characteristics (Normal Mode)

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITION⁽²⁾	TYP	MAX⁽¹⁾	UNIT
I_CC12	Supply voltage, 1.2-V core power	Normal mode	600	1020	mA
_{ICC19_DMD}	Supply voltage, 1.9-V I/O power (DMD LPDDR)	Normal mode	30	50	mA
I_CC33	Supply voltage, 3.3-V (I/O) power	Normal mode	40	70	mA
I_{CC12_FPD}	FPD-Link LVDS I/F supply voltage, 1.2-V power	Normal mode	60	100	mA
I_{CC33_FPD}	FPD-Link LVDS I/F supply voltage, 3.3-V power	Normal mode	50	85	mA
I_{CC12_PLLD}	Supply voltage, PLL digital power (1.2 V)	Normal mode	9	15	mA
I_{CC12_PLLM}	Supply voltage, master clock generator PLL digital power (1.2 V)	Normal mode	9	15	mA
I_{CC18_PLLD}	Supply voltage, PLL analog power (1.8 V)	Normal mode	10	16	mA
I_{CC18_PLLM}	Supply voltage, master clock generator PLL analog power (1.8 V)	Normal mode	10	16	mA
P_TOT	Total power	Normal mode	1225	2200	mW

(1) Maximum power values are estimates and may not reflect the actual final power consumption of DLPC6401 ASIC.

(2) Normal mode refers to ASIC operation during full functionality, active product operation. Typical values correspond to power dissipated on nominal process devices operating at nominal voltage and 70°C junction temperature (approximately 25°C ambient) displaying typical video-graphics content from a high-frequency source. Maximim values correspond to power dissipated on fast process devices operating at high voltage and 105°C junction temperature (approximately 55°C ambient) displaying typical video-graphics content from a high-frequency source. The increased power dissipation observed on fast process devices operated at maximum recommended temperature is primarily a result of increased leakage current.

6.7 System Oscillators Timing Requirements

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
ƒ_clock	Clock frequency, MOSC⁽¹⁾		31.9968	32.0032	MHz
t_c	Cycle time, MOSC⁽¹⁾		31.188	31.256	ns
t_w(H)	Pulse duration⁽²⁾, MOSC, high	50% to 50% reference points (signal)	12.5		ns
t_w(L)	Pulse duration⁽²⁾, MOSC, low	50% to 50% reference points (signal)	12.5		ns
t_t	Transition time⁽²⁾, MOSC, t_t = t_f/ t_r	20% to 80% reference points (signal)		7.5	ns
t_jp	Period jitter⁽²⁾, MOSC (that is, the deviation in period from ideal period due solely to high-frequency jitter – not spread spectrum clocking)		–100	100	ps

(1) The frequency range for MOSC is 32 MHz with ±100 PPM accuracy. (This includes impact to accuracy due to aging, temperature, and trim sensitivity.) The MOSC input cannot support spread spectrum clock spreading.

(2) Applies only when driven by an external digital oscillator.

6.8 Test and Reset Timing Requirements

			MIN	MAX	UNIT
t_W1(L)	Pulse duration, inactive low, PWRGOOD	50% to 50% reference points (signal)	4		µs
t_t1	Transition time, PWRGOOD, t_t1 = t_f / t_r	20% to 80% reference points (signal)		625	µs
t_W2(L)	Pulse duration, inactive low, POSENSE	50% to 50% reference points (signal)	500		µs
t_t2	Transition time, POSENSE, t_t2 = t_f / t_r	20% to 80% reference points (signal)		1	µs
t_PH	Power hold time, POSENSE remains active after PWGOOD is deasserted	20% to 80% reference points (signal)	500		µs

6.9 JTAG Interface: I/O Boundary Scan Application Timing Requirements

			MIN	MAX	UNIT
ƒ_clock	Clock frequency, TCK			10	MHz
t_C	Cycle time, TCK		100		ns
t_W(H)	Pulse duration, high	50% to 50% reference points (signal)	40		ns
t_W(L)	Pulse duration, low	50% to 50% reference points (signal)	40		ns
t_t	Transition time, t_t = t_f / t_r	20% to 80% reference points (signal)		5	ns
t_SU	Setup time, TDI valid before TCK↑		8		ns
t_h	Hold time, TDI valid after TCK↑		2		ns
t_SU	Setup time, TMS1 valid before TCK↑		8		ns
t_h	Hold time, TMS1 valid after TCK↑		2		ns

6.10 Port 1 Input Pixel Interface Timing Requirements

			MIN	MAX	UNIT
ƒ_clock	Clock frequency, P1A_CLK, P1B_CLK, P1C_CLK		12	150	MHz
t_c	Cycle time, P1A_CLK, P1B_CLK, P1C_CLK		6.666	83.33	ns
t_w(H)	Pulse duration, high	50% to 50% reference points (signal)	2.3		ns
t_w(L)	Pulse duration, low	50% to 50% reference points (signal)	2.3		ns
t_jp	Clock period jitter, P1A_CLK, P1B_CLK, P1C_CLK (that is, the deviation in period from ideal period)	Max ƒ_clock		See ⁽²⁾	ps
t_t	Transition time, t_t = t_f / t_r, P1A_CLK, P1B_CLK, P1C_CLK	20% to 80% reference points (signal)	0.6	2	ns
t_t	Transition time, t_t = t_f/ t_r, P1_A(9-0), P1_B(9-0) , P1_C(9-0), P1_HSYNC, P1_VSYNC, P1_DATEN	20% to 80% reference points (signal)	0.6	3	ns
t_t	Transition time, t_t = t_f/ t_r, ALF_HSYNC, ALF_VSYNC, ALF_CSYNC⁽¹⁾	20% to 80% reference points (signal)	0.6	3	ns
SETUP AND HOLD TIMES⁽³⁾
t_su	Setup time, P1_A(9-0), valid before P1x_CLK↑↓		0.8		ns
t_h	Hold time, P1_A(9-0), valid after P1x_CLK↑↓		0.8		ns
t_su	Setup time, P1_B(9-0), valid before P1x_CLK↑↓		0.8		ns
t_h	Hold time, P1_B(9-0), valid after P1x_CLK↑↓		0.8		ns
t_su	Setup time, P1_C(9-0), valid before P1x_CLK↑↓		0.8		ns
t_h	Hold time, P1_C(9-0), valid after P1x_CLK↑↓		0.8		ns
t_su	Setup time, P1_VSYNC, valid before P1x_CLK↑↓		0.8		ns
t_h	Hold time, P1_VSYNC, valid after P1x_CLK↑↓		0.8		ns
t_su	Setup time, P1_HSYNC, valid before P1x_CLK↑↓		0.8		ns
t_h	Hold time, P1_HSYNC, valid after P1x_CLK↑↓		0.8		ns
t_su	Setup time, P1_FIELD, valid before P1x_CLK↑↓		0.8		ns
t_h	Hold time, P1_FIELD, valid after P1x_CLK↑↓		0.8		ns
t_su	Setup time, P1_DATEN, valid before P1x_CLK↑↓		0.8		ns
t_h	Hold time, P1_DATEN, valid after P1x_CLK↑↓		0.8		ns

(1) ALF_CSYNC, ALF_VSYNC and ALF_HSYNC are asynchronous signals.

(2) Use the following formula to obtain the jitter: Maximum clock jitter = ±[(1 / ƒ_clock) – 5414 ps].

(3) Setup and hold times should be considered the same regardless of clock used [P1A_CLK, P1B_CLK, P1C_CLK].

6.11 Port 2 Input Pixel Interface (FPD-Link Compatible LVDS Input) Timing Requirements⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾⁽⁵⁾⁽⁶⁾

		MIN	MAX	UNIT
ƒ_clock	Clock frequency, P2_CLK (LVDS input clock)	20	90	MHz
t_c	Cycle time, P2_CLK (LVDS input clock)	11.1	50	ns
t_slew	Clock or data slew rate (ƒ_pxck< 90 MHz)	0.3		V/ns
t_slew	Clock or data slew rate (ƒ_pxck > 90 MHz)	0.5		V/ns
t_startup	Link start-up time (internal)		1	ms

(1) Minimize crosstalk and match traces on the PCB as close as possible.

(2) Maintain the common mode voltage as close to 1.2 V as possible.

(3) Maintain the absolute input differential voltage as high as possible.

(4) The LVDS open input detection is related to a low common mode voltage only. It is not related to a low-differential swing.

(5) LVDS power 3.3-V supply (VDD33_FPD) noise level should be below 100 mV_PP.

(6) LVDS power 1.2-V supply (VDD12_FPD) noise level should be below 60 mV_PP.

6.12 Synchronous Serial Port (SSP) Interface Timing Requirements

		MIN	MAX	UNIT
t_su	Setup time, SSP0_RXD valid before SSP0_ CLK↓	10		ns
t_h	Hold time, SSP0_RXD valid after SSP0_ CLK↓	10		ns
t_t	Transition time⁽¹⁾, SSP0_RXD, t_t= t_f / t_r		4	ns
t_su	Setup time, SSP1_RXD valid before SSP1_ CLK↓	10		ns
t_h	Hold time, SSP1_RXD valid after SSP1_ CLK↓	10		ns
t_t	Transition time⁽¹⁾, SSP1_RXD, t_t = t_f / t_r		4	ns

(1) 20% to 80% reference points (signal)

6.13 Programmable Output Clocks Switching Characteristics

over operating free-air temperature range, C_L (min timing) = 5 pF, C_L (max timing) = 50 pF (unless otherwise noted) (see Figure 5)

PARAMETER		FROM (INPUT)	TO (OUTPUT)	MIN	MAX	UNIT
ƒ_clock	Clock frequency, OCLKC⁽¹⁾	N/A	OCLKC	0.7759	48	MHz
t_c	Cycle time, OCLKC⁽¹⁾	N/A	OCLKC	20.83	1288.8	ns
t_w(H)	Pulse duration, high 50% to 50% reference points (signal)	N/A	OCLKC	(t_c / 2) – 2		ns
t_w(L)	Pulse duration, low⁽²⁾ 50% to 50% reference points (signal)	N/A	OCLKC	(t_c / 2) – 2		ns
ƒ_clock	Clock frequency, OCLKD⁽¹⁾	N/A	OCLKD	0.7759	48	MHz
t_c	Cycle time, OCLKD	N/A	OCLKD	20.83	1288.8	ns
t_w(H)	Pulse duration, high⁽²⁾ 50% to 50% reference points (signal)	N/A	OCLKD	(t_c / 2) – 2		ns
t_w(L)	Pulse duration, low⁽²⁾ 50% to 50% reference points (signal)	N/A	OCLKD	(t_c / 2) – 2		ns
ƒ_clock	Clock frequency, OCLKE⁽¹⁾	N/A	OCLKE	0.7759	48	MHz
t_c	Cycle time, OCLKE	N/A	OCLKE	20.83	1288.8	ns
t_w(H)	Pulse duration, high⁽²⁾ 50% to 50% reference points (signal)	N/A	OCLKE	(t_c / 2) – 2		ns
t_w(L)	Pulse duration, low⁽²⁾ 50% to 50% reference points (signal)	N/A	OCLKE	(t_c / 2) – 2		ns

(1) The frequency of OCLKC through OCLKE is programmable.

(2) The duty cycle of OCLKC through OCLKE is within ±2 ns of 50%.

6.14 Synchronous Serial Port (SSP) Interface Switching Characteristics

over recommended operating conditions, C_L (min timing) = 5 pF, C_L (max timing) = 35 pF (unless otherwise noted) (see Figure 10)

PARAMETER		FROM (INPUT)	TO (OUTPUT)	MIN	MAX	UNIT
ƒ_clock	Clock frequency, SSP0_CLK ⁽¹⁾⁽²⁾	N/A	SSP0_CLK	0.287	9333	kHz
t_c	Cycle time, SSP0_CLK	N/A	SSP0_CLK	0.107	3483	us
t_w(H)	Pulse duration, high 50% to 50% reference points (signal)	N/A	SSP0_CLK	48		ns
t_w(L)	Pulse duration, low 50% to 50% reference points (signal)	N/A	SSP0_CLK	48		ns
t_pd	Output propagation, clock to Q, SSP0_TXD	SSP0_CLK↑	SSP0_TXD	–5	5	ns
ƒ_clock	Clock frequency, SSP1_CLK ⁽¹⁾⁽²⁾	N/A	SSP1_CLK	2.296	74667	kHz
t_c	Cycle time, SSP1_CLK	N/A	SSP1_CLK	0.013	436	us
t_w(H)	Pulse duration, high 50% to 50% reference points (signal)	N/A	SSP1_CLK	5.85		ns
t_w(L)	Pulse duration, low 50% to 50% reference points (signal)	N/A	SSP1_CLK	5.85		ns
t_pd	Output propagation, clock to Q, SSP1_TXD	SSP1_CLK↑	SSP1_TXD	–2	2	ns

(1) SSP output timing supports both positive and negative clocking polarity. Figure 10 shows only positive clocking polarity. When the clock polarity is configured through software to be negative, the data is transferred and captured on the opposite edge of the clock shown.

(2) The maximum rates shown apply to master mode operation only. Slave mode operation is limited to 1/6 of these rates.