7.3.1.1 Power-Up Reset Operation

Immediately following a power-up event, DLPC6401 hardware automatically brings up the master PLL and places the ASIC in normal power mode. It then follows the standard system reset procedure (see System Reset Operation).

7.3.1.2 System Reset Operation

Immediately following any type of system reset (power-up reset, PWRGOOD reset, watchdog timer timeout, and so on), the DLPC6401 device automatically returns to NORMAL power mode and returns to the following state.

• All GPIO tri-state and as a result, all GPIO-controlled voltage switches default to enabling power to all ASIC supply lines. (Assume these outputs are externally pulled-high.)
• The master PLL remains active (it is reset only after a power-up reset sequence) and most of the derived clocks are active. However, only those resets associated with the ARM9 processor and its peripherals are released. (The ARM9 is responsible for releasing all other resets.)
• ARM9 associated clocks default to their full clock rates. (Boot-up is a full speed.)
• All front-end derived clocks are disabled.
• The PLL feeding the DDR DMD I/F (PLLD) defaults to its power-down mode and all derived clocks are inactive with corresponding resets asserted. (The ARM9 is responsible for enabling these clocks and releasing associated resets.)
• DMD I/O (except DMD_DAD_OEZ) defaults to its outputs in a logic low state. DMD_DAD_OEZ defaults tri-stated, but should be pulled high through an external 30- to 51-kΩ pullup resistor on the PCB.
• All resets output by the DLPC6401 device remain asserted until released by the ARM9 (after boot-up).
• The ARM9 processor boots-up from external flash.

When the ARM9 boots-up, the ARM9 API:

• Configures the programmable DDR clock generator (DCG) clock rates (that is, the DMD LPDDR I/F rate)
• Enables the DCG PLL (PLLD) while holding divider logic in reset
• When the DCG PLL locks, ARM9 software sets DMD clock rates
• API software then releases DCG divider logic resets, which in turn, enable all derived DCG clocks
• Releases external resets

Application software then typically waits for a wake-up command (through the soft power switch on the projector) from the end user. When the projector is requested to wake-up, the software places the ASIC back in normal mode, re-initialize clocks, and resets as required.

• t2: device drives INIT_DONE high within 5 ms after reset is release. Indicates auto-initialization is busy
• t3: I²C or DBI-C access to DLPC6401 device does not start until the INIT_BUSY flag (on INIT_DONE) goes low. This can occur within 100 ms, but may take several seconds
• t5: an active high pulse on INIT_DONE following the initialization period indicates a detected error condition. The device reports the source of the error in the system status.

Figure 12. Internal Memory Test Diagram

7.3.1.3 Spread Spectrum Clock Generator Support

The DLPC6401 device supports limited, internally-controlled, spread spectrum clock spreading on the DMD interface. The purpose is to frequency spread all signals on the high-speed, external interfaces to reduce EMI emissions. Clock spreading is limited to triangular waveforms. The DLPC6401 device provides modulation options of 0%, ±0.5%, and ±1.0% (center-spread modulation).

7.3.1.4 GPIO Interface

The DLPC6401 device provides 38 software-programmable, general-purpose I/O pins. Each GPIO pin is individually configurable as either input or output. In addition, each GPIO output can be either configured as push-pull or open-drain. Some GPIO have one or more alternate-use modes, which are also software configurable. The reset default for all GPIO is as an input signal. However, any alternate function connected to these GPIO pins, with the exception of general-purpose clocks and PWM generation, will be reset. When configured as open-drain, the outputs must be externally pulled-up (to the 3.3-V supply). External pullup or pulldown resistors may be required to ensure stable operation before software is able to configure these ports.

7.3.1.5 Source Input Blanking

Vertical and horizontal blanking requirements for both input ports are defined as follows (see 视频时序参数定义).

• Minimum port 1 vertical blanking:
  • Vertical back porch: 370 µs
  • Vertical front porch: 2 lines
  • Total vertical blanking: 370 µs + 3 lines
• Minimum port 2 vertical blanking:
  • Vertical back porch: 370 µs
  • Vertical front porch: 0 lines
  • Total vertical blanking: 370 µs + 3 lines
• Minimum port 1 and port 2 horizontal blanking:
  • Horizontal back porch (HBP): 10 pixels
  • Horizontal front porch (HFP): 0 pixels
  • Total horizontal blanking (THB):
    • 0.45 WXGA DMD: Roundup (154286 / Source_APPL, 0)
    • 0.4 XGA DMD: Roundup (144686 / Source_APPL, 0) pixels

7.3.1.6 Video and Graphics Processing Delay

The DLPC6401 device introduces a fixed number of field and frame delays. For optimum audio and video synchronization, this delay must be matched in the audio path. Table 3 defines the video delay to support audio matching.

Frame and fields in Table 3 refer to source frames and fields.

Table 4. Wait State Program Values for Typical Flash Access Times

Table 5. Typical GPIO_16 and GPIO_17 Pin Configurations for Various Flash Sizes

7.3.2.1 Calibration and Debug Support

The DLPC6401 device contains a test point output port, TSTPT_(7:0), which provides selected system calibration support as well as ASIC debug support. These test points are inputs while reset is applied and switch to outputs when reset is released. The state of these signals is sampled upon the release of system reset and the captured value configures the test mode until the next time reset is applied. Each test point includes an internal pulldown resistor and thus external pullups are used to modify the default test configuration. The default configuration (x00) corresponds to the TSTPT(7:0) outputs being driven low for reduce switching activity during normal operation. For maximum flexibility, TI recommends an option to jumper to an external pullup for TSTPT(0). Note that adding a pullup to TSTPT(7:1) may have adverse affects for normal operation and TI does not recommend it. Note that these external pullups are sampled only after a 0-to-1 transition on POSENSE and thus changing their configuration after reset has been released does not have any affect until the next time reset is asserted and released. Table 6 defines the test mode selection for two programmable scenarios defined by TSTPT_(0):

7.3.2.2 Board-Level Test Support

The in-circuit tri-state enable signal (ICTSEN) is a board-level test control signal. By driving ICTSEN to a logic-high state, all ASIC outputs (except TDO1 and TDO2) are tri-stated.

The DLPC6401 device also provides JTAG boundary scan support on all I/O signals, non-digital I/O, and a few special signals. Table 7 defines these exceptions.