ZHCSNH1C May   2021  – November 2022 DLPC6540

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Electrical Characteristics
    6. 6.6  Pin Electrical Characteristics
    7. 6.7  DMD HSSI Electrical Characteristics
    8. 6.8  DMD Low-Speed LVDS Electrical Characteristics
    9. 6.9  V-by-One Interface Electrical Characteristics
    10. 6.10 USB Electrical Characteristics
    11. 6.11 System Oscillator Timing Requirements
    12. 6.12 Power Supply and Reset Timing Requirements
    13. 6.13 DMD HSSI Timing Requirements
    14. 6.14 DMD Low-Speed LVDS Timing Requirements
    15. 6.15 V-by-One Interface General Timing Requirements
    16. 6.16 Source Frame Timing Requirements
    17. 6.17 Synchronous Serial Port Interface Timing Requirements
    18. 6.18 Master and Slave I2C Interface Timing Requirements
    19. 6.19 Programmable Output Clock Timing Requirements
    20. 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
    21. 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
    22. 6.22 Multi-Trace ETM Interface Timing Requirements
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Sources
      2. 7.3.2 Processing Delays
      3. 7.3.3 V-by-One Interface
      4. 7.3.4 DMD (HSSI) Interface
      5. 7.3.5 Program Memory Flash Interface
      6. 7.3.6 GPIO Supported Functionality
      7. 7.3.7 Debug Support
    4. 7.4 Device Operational Modes
      1. 7.4.1 Standby Mode
      2. 7.4.2 Active Mode
        1. 7.4.2.1 Normal Configuration
  8. Power Supply Recommendations
    1. 8.1 Power Supply Management
    2. 8.2 Hot Plug Usage
    3. 8.3 Power Supplies for Unused Input Source Interfaces
    4. 8.4 Power Supplies
      1. 8.4.1 1.15-V Power Supplies
      2. 8.4.2 1.21V Power Supply
      3. 8.4.3 1.8-V Power Supplies
      4. 8.4.4 3.3-V Power Supplies
  9. Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 General Layout Guidelines
      2. 9.1.2 Power Supply Layout Guidelines
      3. 9.1.3 Layout Guidelines for Internal Controller PLL Power
      4. 9.1.4 Layout Guideline for DLPC6540 Reference Clock
        1. 9.1.4.1 Recommended Crystal Oscillator Configuration
      5. 9.1.5 V-by-One Interface Layout Considerations
      6. 9.1.6 USB Interface Layout Considerations
      7. 9.1.7 DMD Interface Layout Considerations
      8. 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
      9. 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
    2. 9.2 Thermal Considerations
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方米6体育平台手机版_好二三四免责声明
      2. 10.1.2 Device Nomenclature
        1. 10.1.2.1 Device Markings
        2. 10.1.2.2 Package Data
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 术语表
      1. 10.6.1 Video Timing Parameter Definitions
  11. 11Mechanical, Packaging, and Orderable Information
    1.     79

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DMD (HSSI) Interface

The DLPC6540 Controller DMD interface supports two High Speed Serial Interface (HSSI) output-only interfaces for data transmission, a single low speed LVDS output-only interface for command write transactions, as well as a low speed single-ended input interface used for command read transactions. Each HSSI port supports full data-only inter-lane remapping within the port, but not between ports. When utilizing this feature, each unique data lane pair can only be mapped to one unique destination data lane pair, and Intra-lane remapping (i.e. swapping P with N) is not supported. In addition, the two HSSI ports can also be swapped. Lane and port remapping (specified in flash) can help with board layout as needed. The number of HSSI ports and number of HSSI lanes/per HSSI port required are based on DMD type and DMD display resolution. Table 7-15 shows some remapping examples. When both ports are used, they do not need to have the same pin mapping.

Table 7-15 Controller to DMD Pin Mapping Examples
DLPC6540 Controller PINS - REMAPPING EXAMPLES TO DMD PINSDMD PINS
BASELINEFLIP HSSI0 180
No FLIP HSSI1
SWAP HSSI0 PORT WITH HSSI1 PORTSWAP HSSI0 PORT WITH HSSI1 PORT AND MIXED REMAPPING
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI1_D0_P
DMD_HSSI1_D0_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI1_D1_P
DMD_HSSI1_D1_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI1_D2_P
DMD_HSSI1_D2_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI1_D3_P
DMD_HSSI1_D3_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI0_D4_P
DMD_HSSI0_D4_N
DMD_HSSI0_D2_P
DMD_HSSI0_D2_N
DMD_HSSI1_D4_P
DMD_HSSI1_D4_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI0_D5_P
DMD_HSSI0_D5_N
DMD_HSSI0_D3_P
DMD_HSSI0_D3_N
DMD_HSSI1_D5_P
DMD_HSSI1_D5_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI0_D6_P
DMD_HSSI0_D6_N
DMD_HSSI0_D0_P
DMD_HSSI0_D0_N
DMD_HSSI1_D6_P
DMD_HSSI1_D6_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N
DMD_HSSI0_D7_P
DMD_HSSI0_D7_N
DMD_HSSI0_D1_P
DMD_HSSI0_D1_N
DMD_HSSI1_D7_P
DMD_HSSI1_D7_N