ZHCSNH1C May 2021 – November 2022 DLPC6540
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Power Electrical Characteristics
- 6.6 Pin Electrical Characteristics
- 6.7 DMD HSSI Electrical Characteristics
- 6.8 DMD Low-Speed LVDS Electrical Characteristics
- 6.9 V-by-One Interface Electrical Characteristics
- 6.10 USB Electrical Characteristics
- 6.11 System Oscillator Timing Requirements
- 6.12 Power Supply and Reset Timing Requirements
- 6.13 DMD HSSI Timing Requirements
- 6.14 DMD Low-Speed LVDS Timing Requirements
- 6.15 V-by-One Interface General Timing Requirements
- 6.16 Source Frame Timing Requirements
- 6.17 Synchronous Serial Port Interface Timing Requirements
- 6.18 Master and Slave I2C Interface Timing Requirements
- 6.19 Programmable Output Clock Timing Requirements
- 6.20 JTAG Boundary Scan Interface Timing Requirements (Debug Only)
- 6.21 JTAG ARM Multi-Ice Interface Timing Requirements (Debug Only)
- 6.22 Multi-Trace ETM Interface Timing Requirements
- 7 Detailed Description
- 8 Power Supply Recommendations
-
9 Layout
- 9.1
Layout Guidelines
- 9.1.1 General Layout Guidelines
- 9.1.2 Power Supply Layout Guidelines
- 9.1.3 Layout Guidelines for Internal Controller PLL Power
- 9.1.4 Layout Guideline for DLPC6540 Reference Clock
- 9.1.5 V-by-One Interface Layout Considerations
- 9.1.6 USB Interface Layout Considerations
- 9.1.7 DMD Interface Layout Considerations
- 9.1.8 General Handling Guidelines for Unused CMOS-Type Pins
- 9.1.9 Maximum Pin-to-Pin, PCB Interconnects Etch Lengths
- 9.2 Thermal Considerations
- 9.1
Layout Guidelines
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
9.1.7 DMD Interface Layout Considerations
The DLPC6540 controller HSSI differential interface waveform quality and timing is dependent on the total length of the interconnect system, the spacing between traces, the characteristic impedance, etch losses, and how well matched the lengths are across the interface. Thus, ensuring positive timing margin requires attention to many factors.
DLPC6540 I/O timing parameters as well as DMD I/O timing parameters can be found in their corresponding data sheets. Similarly, PCB routing mismatch can be budgeted and met through controlled PCB routing. PCB design recommendations are provided in Table 9-7, Figure 9-15, and the paragraph below as a starting point for the customer.
Table 9-7 PCB Recommendations for DMD Interface
(1)(2)
| PARAMETER | MIN | MAX | UNIT | |
|---|---|---|---|---|
| TW | Trace Width | 5.7 | mils | |
| TS | Intra-lane Trace Spacing | 5.3 | mils | |
| TSPP | Inter-lane trace spacing (3) | 48.3 | mils | |
(1) Recommendations to achieve the desired nominal differential impedance as specified by RDIFF in Section 6.7.
(2) These parameters show recommendations based on the micro-strip design
shown in Figure 9-15. This design minimizes signal loss to support longer trace lengths at the
expense of electromagnetic interference (EMI). The designer has the option to
use of a stripline design for shorter trace lengths and to target minimizing EMI
at the expense of signal loss.
(3) A reduced inter-lane spacing can be used to escape the Controller ball field,
however, widen this spacing to at least the stated minimum after escape.
Figure 9-15 DMD Differential Layout RecommendationsAdditional DMD interface layout guidelines:
- Route the differential signal pairs on the top layer of the PBC to minimize the number of vias. Limit the number of necessary vias to two. If two are required, place one at each end of the line (one at the controller and one at the DMD).
- Route the differential signal pairs over a single ground or power plane using a Micro-strip line configuration.
- Do not route the differential signal pairs over the slit of power or ground planes.
- Ensure the bend angles associated with the differential signal pairs are between 135o and 225o.
- Route the single-ended signal in a way that to minimizes the number of vias required. Limit the number of necessary vias to two. If two are required, place one at each end of the line (one at the controller and one at the DMD).
- Avoid stubs.
- No external termination resistors are required on the DMD_HSSI or DMD_LS differential signals.
- Include a series termination resistor (with a value of 30.1 Ω, for example) to the DMD_LS0_RDATA and DMD_LS1_RDATA single-ended signal paths. Place the resistor as close as possible to the corresponding DMD pin.
- The DMD_DEN_ARSTZ does not typically require a series resistor, however, for a long trace, one might be needed to reduce undershoot or overshoot.