米6体育平台手机版

ZHCSD20H October 2014 – June 2024 DLPC900

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

ZPC|516
- MPBGAJ0

散热焊盘机械数据 (封装 | 引脚)

订购信息

zhcsd20h_oa

5.15 DMD LVDS Interface Switching Characteristics

Switching characteristics over recommended operating conditions ⁽¹⁾ ⁽²⁾ ⁽³⁾ ⁽⁴⁾ ⁽⁵⁾ ⁽⁶⁾

PARAMETER		FROM (INPUT)	TO (OUTPUT)	MIN	MAX	UNIT
ƒ_clock	Clock frequency, DCK_A	N/A	DCK_A	100	400	MHz
t_c	Cycle time, DCK_A1	N/A	DCK_A	2475.3		ps
t_w(H)	Pulse duration, high 5 (50% to 50% reference points)	N/A	DCK_A	1093		ps
t_w(L)	Pulse duration, low 5 (50% to 50% reference points)	N/A	DCK_A	1093		ps
t_t	Transition time, t_t = t_ƒ / t_r (20% to 80% reference points)	N/A	DCK_A	100	400	ps
t_osu	Output setup time at max clock rate3	DCK_A↑↓	SCA, DDA(15:0)	438		ps
t_oh	Output hold time at max clock rate3	DCK_A↑↓	SCA, DDA(15:0)	438		ps
ƒ_clock	Clock frequency, DCK_B	N/A	DCK_B	100	400	MHz
t_c	Cycle time, DCK_B1	N/A	DCK_B	2475.3		ps
t_w(H)	Pulse duration, high 5 (50% to 50% reference points)	N/A	DCK_B	1093		ps
t_w(L)	Pulse duration, low 5 (50% to 50% reference points)	N/A	DCK_B	1093		ps
t_t	Transition time, t_t = t_ƒ / t_r (20% to 80% reference points)	N/A	DCK_B	100	400	ps
t_osu	Output setup time at max clock rate3	DCK_B↑↓	SCB, DDB(15:0)	438		ps
t_oh	Output hold time at max clock rate3	DCK_B↑↓	SCB, DDB(15:0)	438		ps
t_sk	Output skew, channel A to channel B	DCK_A↑	DCK_B↑		250	ps

(1) The minimum cycle time (t_c) for DCK_A and DCK_B includes 1.0% spread spectrum modulation.

(2) The DMD LVDS interface uses a double data rate (DDR) clock, thus both rising and falling edges of DCK_A and DCK_B are used to clock data into the DMD. As a result, the minimum t_w(H) and t_w(L) parameters determine the worse-case DDR clock cycle time.

(3) Output setup and hold times for DMD clock frequencies below the maximum can be calculated as follows:
t_osu(ƒ_clock) = t_osu(ƒ_max) + 250000 × (1 / ƒ_clock – 1 / 400) and t_oh(ƒ_clock) = t_oh(ƒ_max) + 250000 × (1 / ƒ_clock – 1 / 400) where ƒ_clock is in MHz.

(4) The DLPC900 is a full-bus DMD signaling interface. Figure 6-4 shows the controller connections for this configuration.

(5) The pulse duration minimum for any clock rate can be calculated using the following formulas.

Pulse duration minimum when using spread spectrum
1. Duty cycle % = 49.06 – [0.01335 × clock frequency (MHz)]
2. Minimum pulse duration = 1 / clock frequency × DC%
  1. Example: At 400MHz: DC% = 49.06 – [0.01335 × 400] = 43.72%
  2. MPW = 1 / 400MHz × 0.4372 = 1093.0ps
Pulse duration minimum when not using spread spectrum
1. Duty cycle % = 49.00 – [0.01055 × clock frequency (MHz)]
2. Minimum pulse duration = 1 / clock frequency × DC%
  1. Example: At 400MHz: DC% = 49.00 – [0.01055 × 400] = 44.78%
  2. MPW = 1 / 400MHz × 0.448 = 1119.5ps

(6) A duty cycle specification is not provided because the key limiting factor to clock frequency is the minimum pulse duration (that is, if the other half of the clock period is larger than the minimum, it is not limiting the clock frequency).

Figure 5-13 DMD LVDS Interface