Although the DLPC900 requires an array of power supply voltages, for example, 1.15V, 1.8V, and 3.3V, there are no restrictions regarding the relative order of power supply sequencing to avoid damaging the DLPC900, as long as the system is held in reset during power supply sequencing. This is true for both power-up (reset controlled by POSENSE) and power-down (reset controlled by PWRGOOD) scenarios. Similarly, there is no minimum time between powering-up or powering-down the different supplies feeding the DLPC900. However, power-sequencing requirements are common for the devices that share the supplies with the DLPC900.

Power-sequencing recommendations to ensure proper operation are:

• 1.15V core power must be applied whenever any I/O power is applied. This ensures the state of the associated I/O that are powered are set to a known state. Thus, applying core power first is recommended.
• All DLPC900 power must be applied before POSENSE is asserted to ensure proper power-up initialization is performed.

It is assumed that all DLPC900 power-up sequencing is handled by external hardware. It is also assumed that an external power monitor will hold the DLPC900 in system reset during power-up (that is, POSENSE = 0). During this time, all controller I/Os are tristated. The primary PLL (PLLM1) will be released from reset upon the low-to-high transition of POSENSE, but the DLPC900 will be kept in reset for an additional 60ms to allow the PLL to lock and stabilize its outputs. After this delay the DLPC900 internal resets will be deasserted, thus causing the processor to begin its boot-up routine.

Figure 8-2 shows the recommended DLPC900 system power-up sequence of the regulators:

Figure 8-2 Power Sequencing