ZHCSD20H October 2014 – June 2024 DLPC900
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics
- 5.6 System Oscillators Timing Requirements #GUID-909D0FD3-84C7-4481-924A-4FDE7EB548A1/DLPS0373944
- 5.7 Power-Up and Power-Down Timing Requirements
- 5.8 JTAG Interface: I/O Boundary Scan Application Timing Requirements
- 5.9 JTAG Interface: I/O Boundary Scan Application Switching Characteristics
- 5.10 Programmable Output Clocks Switching Characteristics
- 5.11 Port 1 and 2 Input Pixel Interface Timing Requirements
- 5.12 Two Pixels Per Clock (48-Bit Bus) Timing Requirements
- 5.13 Synchronous Serial Port (SSP) Switching Characteristics
- 5.14 DMD Interface Switching Characteristics
- 5.15 DMD LVDS Interface Switching Characteristics
- 5.16 Source Input Blanking Requirements
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 DMD Configurations
- 6.3.2 Video Timing Input Blanking Specification
- 6.3.3 Board-Level Test Support
- 6.3.4 Two Controller Considerations
- 6.3.5 Memory Design Considerations
- 6.4 Device Functional Modes
-
7 Application and Implementation
- 7.1 Application Information
- 7.2
Typical Applications
- 7.2.1 Typical Two Controller Chipset
- 7.2.2 Typical Single Controller Chipset
- 8 Power Supply Recommendations
-
9 Layout
- 9.1
Layout Guidelines
- 9.1.1 General PCB Recommendations
- 9.1.2 PCB Layout Guidelines for Internal Controller PLL Power
- 9.1.3 PCB Layout Guidelines for Quality Video Performance
- 9.1.4 Recommended MOSC Crystal Oscillator Configuration
- 9.1.5 Spread Spectrum Clock Generator Support
- 9.1.6 GPIO Interface
- 9.1.7 General Handling Guidelines for Unused CMOS-Type Pins
- 9.1.8 DMD Interface Considerations
- 9.1.9 PCB Design Standards
- 9.1.10 Signal Layers
- 9.1.11 Trace Widths and Minimum Spacing
- 9.1.12 Trace Impedance and Routing Priority
- 9.1.13 Power and Ground Planes
- 9.1.14 Power Vias
- 9.1.15 Decoupling
- 9.1.16 Fiducials
- 9.2 Layout Example
- 9.3 Thermal Considerations
- 9.1
Layout Guidelines
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
9.1.8 DMD Interface Considerations
High-speed interface waveform quality and timing on the DLPC900 controller (that is, the LVDS DMD interface) is dependent on the following factors:
- Total length of the interconnect system
- Spacing between traces
- Characteristic impedance
- Etch losses
- How well matched the lengths are across the interface
Thus, ensuring positive timing margin requires attention to many factors.
As an example, DMD interface system timing margin can be calculated as follows:
The PCB SI degradation is the signal integrity degradation due to PCB affects which includes such things as simultaneously switching output (SSO) noise, crosstalk, and intersymbol interference (ISI) noise.
DLPC900 I/O timing parameters, as well as DMD I/O timing parameters, can be easily found in their corresponding data sheets. Similarly, PCB routing mismatch can be easily budgeted and met via controlled PCB routing. However, PCB SI degradation is not as easy-to-determine.
In an attempt to minimize the signal integrity analysis that would otherwise be required, the following PCB design guidelines provide a reference of an interconnect system that satisfies both waveform quality and timing requirements (accounting for both PCB routing mismatch and PCB SI degradation). Deviation from these recommendations can work, but must be confirmed with PCB signal integrity analysis or lab measurements.
| PCB design: Refer to the Figure 9-5. | |||
| Configuration: Etch thickness (T): Flex etch thickness (T): Single-ended signal impedance: Differential signal impedance: | Asymmetric dual stripline 1.0oz copper (1.2mil) 0.5oz copper (0.6mil) 50Ω (±10%) 100Ω (±10%) | ||
| PCB stackup: Refer to the Figure 9-5. | |||
| Reference plane 1 is assumed to be a ground plane for proper return path. | |||
| Reference plane 2 is assumed to be the I/O power plane or ground. | |||
| Dielectric FR4, (Er): | 4.2 (nominal) | ||
| Signal trace distance to reference plane 1 (H1): | 5.0mil (nominal) | ||
| Signal trace distance to reference plane 2 (H2): | 34.2mil (nominal) | ||
Figure 9-5 PCB Stackup Geometries| PARAMETER | APPLICATION | SINGLE-ENDED SIGNALS | DIFFERENTIAL PAIRS | UNIT |
|---|---|---|---|---|
| Line width (W) | Escape routing in ball field | 4 (0.1) | 4 (0.1) | mil (mm) |
| PCB etch data or control | 7 (0.18) | 4.25 (0.11) | mil (mm) | |
| PCB etch clocks | 7 (0.18) | 4.25 (0.11) | mil (mm) | |
| Differential signal pair spacing (S) | PCB etch data or control | N/A | 5.75 (1) (0.15) | mil (mm) |
| PCB etch clocks | N/A | 5.75 (1) (0.15) | mil (mm) | |
| Minimum differential pair-to-pair spacing (S) | PCB etch data or control | N/A | 20 (0.51) | mil (mm) |
| PCB etch clocks | N/A | 20 (0.51) | mil (mm) | |
| Minimum line spacing to other signals (S) | Escape routing in ball field | 4 (0.1) | 4 (0.1) | mil (mm) |
| PCB etch data or control | 10 (0.25) | 20 (0.51) | mil (mm) | |
| PCB etch clocks | 20 (0.51) | 20 (0.51) | mil (mm) | |
| Maximum differential pair P-to-N length mismatch | Total data | N/A | 12 (0.3) | mil (mm) |
| Total clock | N/A | 12 (0.3) | mil (mm) |
| SIGNAL GROUP LENGTH MATCHING | ||||
|---|---|---|---|---|
| INTERFACE | SIGNAL GROUP | REFERENCE SIGNAL | MAX MISMATCH | UNIT |
| DMD (LVDS) | SCA_P/ SCA_N DDA_P_(15:0)/ DDA_N_(15:0) | DCKA_P/ DCKA_N | ± 150 (± 3.81) | mil (mm) |
| DMD (LVDS) | SCB_P/ SCB_N DDB_P_(15:0)/ DDB_N_(15:0) | DCKB_P/ DCKB_N | ± 150 (± 3.81) | mil (mm) |
When routing the DMD Interface signals it is recommended to:
- Minimize the number of layer changes for single-ended signals.
- Individual differential pairs can be routed on different layers but the signals of a given pair must not change layers.
| BUS | MIN | MAX | UNIT |
|---|---|---|---|
| DMD (LVDS) | 50 | 375 | mm |
Stubs: Avoid stubs.
Termination Requirements: DMD interface: None – The DMD receiver is differentially terminated to 100Ω internally.
Connector (DMD-LVDS interface bus only):
High-speed connectors that meet the following requirements can be used:
- Differential crosstalk: < 5%
- Differential impedance: 75Ω to 125Ω
Routing requirements for right-angle connectors: When using right-angle connectors, P-N pairs must be routed in the same row to minimize delay mismatch. When using right-angle connectors, propagation delay difference for each row must be accounted for on associated PCB etch lengths.
These guidelines will produce a maximum PCB routing mismatch of 4.41mm (0.174 inch) or approximately 30.4ps, assuming 175ps/inch FR4 propagation delay.
These PCB routing guidelines will result in approximately 25ps system setup margin and 25ps system hold margin for the DMD interface after accounting for signal integrity degradation as well as routing mismatch.
Both the DLPC900 output timing parameters and the DMD input timing parameters include timing budget to account for their respective internal package routing skew.