米6体育平台手机版

ZHCSE90D September 2015 – September 2020 DLPC910

PRODUCTION DATA

6.6 Timing Requirements

(see ⁽¹⁾)

				MIN	NOM	MAX	UNIT
f_cd	Clock frequency, DCLKIN_n ⁽²⁾					400	MHz
f_cd	Clock frequency, DCLKIN_n ⁽²⁾					480	MHz
f_cr	Clock frequency, CLK_R				50		MHz
t_c	Cycle time, DCLKIN_n		f_cd = 400 MHz			2.5	ns
t_c	Cycle time, DCLKIN_n		f_cd = 480 MHz			2.083	ns
t_w(H)	Pulse duration, high	50% to 50% reference points (signal)	f_cd = 400 MHz			1.25	ns
t_w(H)	Pulse duration, high	50% to 50% reference points (signal)	f_cd = 480 MHz			1.042	ns
t_w(L)	Pulse duration, low	50% to 50% reference points (signal)	f_cd = 400 MHz			1.25	ns
t_w(L)	Pulse duration, low	50% to 50% reference points (signal)	f_cd = 480 MHz			1.042	ns
t_t	Transition time, tt = tf /tr	20% to 80% reference points (signal)	f_cd = 400 MHz			0.6	ns
t_t	Transition time, tt = tf /tr	20% to 80% reference points (signal)	f_cd = 480 MHz			0.5	ns
t_jp	Period Jitter DCLKIN_n ⁽³⁾				100		ps
t_sk	Skew, DIN_A(15-0) to DCLKIN_A			-100		100	ps
	Skew, DIN_B(15-0) to DCLKIN_B			-100		100
	Skew, DIN_C(15-0) to DCLKIN_C			-100		100
	Skew, DIN_D(15-0) to DCLKIN_D			-100		100
	Skew, DVALID_n to DCLKIN_n↑			-100		100
	Skew, BLKMD BLKAD to DCLKIN_n↑ ⁽⁴⁾			-100		100
	Skew, ROWMD or ROWAD to DCLKIN_n↑ ⁽⁴⁾			-100		100
	Skew, STEPVCC to DCLKIN↑ ⁽⁴⁾			-100		100

(1) It is recommended that the COMP_DATA, NS_FLIP and RST2BLK flags be set to one value and not adjusted during normal system operation.

(2) Preferred DDC_DCLK _n duty cycle = 50%

(3) This is the deviation in period from ideal period due solely to high frequency jitter.

(4) First edge of DDC_DIN*, ROW*, and BLK* should be synchronous to DVALID rising edge.

Figure 6-1 Input Interface Timing

Note: Dynamic changes to RST2BLK, NS_FLIP and COMP_DATA during normal operation are not recommended.