ZHCSE90D September 2015 – September 2020 DLPC910
PRODUCTION DATA
All register addresses are 32-bit in size, where each register contains a 32-bit value. The actual valid bits are shown in each respective register. Most registers contain spare or unused bits. These bits should be treated as don't-care during a read operation unless otherwise specified. When writing to spare or unused bits, these bits MUST be set to 0. Both the register address and the data require the least-significant byte to be first and most-significant byte last. A SUB CMD must precede the register address to indicate the type of operation, where a 0xF1 indicates a write operation and a 0xF2 indicates a read operation. The following figures show examples of writing and reading to the DESTOP_BUS_SWAP register.
Figure 7-4 shows an I2C master writing data to the DLPC910, where 0xF1 is required as the SUB CMD followed by the register address and finally the register data.
Figure 7-5 shows an I2C master reading data from the DLPC910, where 0xF2 is required as the SUB CMD followed by the register address. Then the master performs STOP followed by a START to read the register data.