ZHCSG69E November   2016  – May 2018 DM505

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Device Comparison Table
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  SD_DAC
      4. 4.3.4  ADC
      5. 4.3.5  Camera Control
      6. 4.3.6  CPI
      7. 4.3.7  CSI2
      8. 4.3.8  EMIF
      9. 4.3.9  GPMC
      10. 4.3.10 Timers
      11. 4.3.11 I2C
      12. 4.3.12 UART
      13. 4.3.13 McSPI
      14. 4.3.14 QSPI
      15. 4.3.15 McASP
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 SDIO Controller
      19. 4.3.19 GPIO
      20. 4.3.20 ePWM
      21. 4.3.21 Emulation and Debug Subsystem
      22. 4.3.22 System and Miscellaneous
        1. 4.3.22.1 Sysboot
        2. 4.3.22.2 Power, Reset and Clock Management (PRCM)
        3. 4.3.22.3 Enhanced Direct Memory Access (EDMA)
        4. 4.3.22.4 Interrupt Controllers (INTC)
      23. 4.3.23 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. Table 5-6   LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7   Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8   IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9   IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS Analog OSC Buffers DC Electrical Characteristics
      6. Table 5-11 LVCMOS CSI2 DC Electrical Characteristics
      7. Table 5-12 Dual Voltage LVCMOS DC Electrical Characteristics
      8. Table 5-13 Analog-to-Digital ADC Subsystem Electrical Specifications
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Timing Requirements and Switching Characteristics
      1. 5.9.1 Timing Parameters and Information
        1. 5.9.1.1 Parameter Information
          1. 5.9.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.9.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.9.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.9.2 Interface Clock Specifications
        1. 5.9.2.1 Interface Clock Terminology
        2. 5.9.2.2 Interface Clock Frequency
      3. 5.9.3 Power Supply Sequences
      4. 5.9.4 Clock Specifications
        1. 5.9.4.1 Input Clocks / Oscillators
          1. 5.9.4.1.1 OSC0 External Crystal
          2. 5.9.4.1.2 OSC0 Input Clock
          3. 5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.9.4.1.3.1 OSC1 External Crystal
            2. 5.9.4.1.3.2 OSC1 Input Clock
          4. 5.9.4.1.4 RC On-die Oscillator Clock
        2. 5.9.4.2 Output Clocks
        3. 5.9.4.3 DPLLs, DLLs
          1. 5.9.4.3.1 DPLL Characteristics
          2. 5.9.4.3.2 DLL Characteristics
            1. 5.9.4.3.2.1 DPLL and DLL Noise Isolation
      5. 5.9.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.9.6 Peripherals
        1. 5.9.6.1  Timing Test Conditions
        2. 5.9.6.2  VIP
        3. 5.9.6.3  DSS
        4. 5.9.6.4  ISS
          1. 5.9.6.4.1 CSI-2 MIPI D-PHY—1.5 V and 1.8 V
        5. 5.9.6.5  EMIF
        6. 5.9.6.6  GPMC
          1. 5.9.6.6.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.9.6.6.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.9.6.6.3 GPMC/NAND Flash Interface Asynchronous Timing
        7. 5.9.6.7  GP Timers
          1. 5.9.6.7.1 GP Timer Features
        8. 5.9.6.8  I2C
          1. Table 5-41 Timing Requirements for I2C Input Timings
          2. Table 5-42 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        9. 5.9.6.9  UART
          1. Table 5-43 Timing Requirements for UART
          2. Table 5-44 Switching Characteristics Over Recommended Operating Conditions for UART
        10. 5.9.6.10 McSPI
        11. 5.9.6.11 QSPI
        12. 5.9.6.12 McASP
          1. Table 5-52 Timing Requirements for McASP1
          2. Table 5-53 Timing Requirements for McASP2
          3. Table 5-54 Timing Requirements for McASP3
          4. Table 5-55 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-56 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-57 Switching Characteristics Over Recommended Operating Conditions for McASP3
        13. 5.9.6.13 DCAN and MCAN
          1. 5.9.6.13.1  DCAN
          2. 5.9.6.13.2  MCAN
          3. Table 5-60 Timing Requirements for CAN Receive
          4. Table 5-61 Switching Characteristics Over Recommended Operating Conditions for CAN Transmit
        14. 5.9.6.14 GMAC_SW
          1. 5.9.6.14.1 GMAC MDIO Interface Timings
          2. 5.9.6.14.2 GMAC RGMII Timings
            1. Table 5-65 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-66 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-67 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-68 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        15. 5.9.6.15 SDIO Controller
          1. 5.9.6.15.1 MMC, SD Default Speed
          2. 5.9.6.15.2 MMC, SD High Speed
          3. 5.9.6.15.3 MMC, SD and SDIO SDR12 Mode
          4. 5.9.6.15.4 MMC, SD SDR25 Mode
        16. 5.9.6.16 GPIO
      7. 5.9.7 Emulation and Debug Subsystem
        1. 5.9.7.1 JTAG Electrical Data/Timing
          1. Table 5-79 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 5-80 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 5-81 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 5-82 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.9.7.2 Trace Port Interface Unit (TPIU)
          1. 5.9.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  DSP Subsystem
    4. 6.4  IPU
    5. 6.5  EVE
    6. 6.6  Memory Subsystem
      1. 6.6.1 EMIF
      2. 6.6.2 GPMC
      3. 6.6.3 ELM
      4. 6.6.4 OCMC
    7. 6.7  Interprocessor Communication
      1. 6.7.1 Mailbox
      2. 6.7.2 Spinlock
    8. 6.8  Interrupt Controller
    9. 6.9  EDMA
    10. 6.10 Peripherals
      1. 6.10.1  VIP
      2. 6.10.2  DSS
      3. 6.10.3  ADC
      4. 6.10.4  ISS
      5. 6.10.5  Timers
        1. 6.10.5.1 General-Purpose Timers
        2. 6.10.5.2 32-kHz Synchronized Timer (COUNTER_32K)
      6. 6.10.6  I2C
      7. 6.10.7  UART
        1. 6.10.7.1 UART Features
      8. 6.10.8  McSPI
      9. 6.10.9  QSPI
      10. 6.10.10 McASP
      11. 6.10.11 DCAN
      12. 6.10.12 MCAN
      13. 6.10.13 GMAC_SW
      14. 6.10.14 SDIO
      15. 6.10.15 GPIO
      16. 6.10.16 ePWM
      17. 6.10.17 eCAP
      18. 6.10.18 eQEP
    11. 6.11 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1  Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2  Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3  Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_dspeve Example Analysis
    4. 7.4  Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
        1. 7.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):
        2. 7.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1):
    5. 7.5  Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 CSI2 Board Design and Routing Guidelines
        1. 7.5.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.2.1.1 General Guidelines
          2. 7.5.2.1.2 Length Mismatch Guidelines
            1. 7.5.2.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.2.1.3 Frequency-domain Specification Guidelines
    6. 7.6  Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7  LPDDR2 Board Design and Layout Guidelines
      1. 7.7.1 LPDDR2 Board Designs
      2. 7.7.2 LPDDR2 Device Configurations
      3. 7.7.3 LPDDR2 Interface
        1. 7.7.3.1 LPDDR2 Interface Schematic
        2. 7.7.3.2 Compatible JEDEC LPDDR2 Devices
        3. 7.7.3.3 LPDDR2 PCB Stackup
        4. 7.7.3.4 LPDDR2 Placement
        5. 7.7.3.5 LPDDR2 Keepout Region
        6. 7.7.3.6 LPDDR2 Net Classes
        7. 7.7.3.7 LPDDR2 Signal Termination
        8. 7.7.3.8 LPDDR2 DDR_VREF Routing
      4. 7.7.4 Routing Specification
        1. 7.7.4.1 DQS[x] and DQ[x] Routing Specification
        2. 7.7.4.2 CK and ADDR_CTRL Routing Specification
    8. 7.8  DDR2 Board Design and Layout Guidelines
      1. 7.8.1 DDR2 General Board Layout Guidelines
      2. 7.8.2 DDR2 Board Design and Layout Guidelines
        1. 7.8.2.1 Board Designs
        2. 7.8.2.2 DDR2 Interface
          1. 7.8.2.2.1  DDR2 Interface Schematic
          2. 7.8.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.8.2.2.3  PCB Stackup
          4. 7.8.2.2.4  Placement
          5. 7.8.2.2.5  DDR2 Keepout Region
          6. 7.8.2.2.6  Bulk Bypass Capacitors
          7. 7.8.2.2.7  High-Speed Bypass Capacitors
          8. 7.8.2.2.8  Net Classes
          9. 7.8.2.2.9  DDR2 Signal Termination
          10. 7.8.2.2.10 VREF Routing
        3. 7.8.2.3 DDR2 CK and ADDR_CTRL Routing
    9. 7.9  DDR3 Board Design and Layout Guidelines
      1. 7.9.1 DDR3 General Board Layout Guidelines
      2. 7.9.2 DDR3 Board Design and Layout Guidelines
        1. 7.9.2.1  Board Designs
        2. 7.9.2.2  DDR3 Device Combinations
        3. 7.9.2.3  DDR3 Interface Schematic
          1. 7.9.2.3.1 32-Bit DDR3 Interface
          2. 7.9.2.3.2 16-Bit DDR3 Interface
        4. 7.9.2.4  Compatible JEDEC DDR3 Devices
        5. 7.9.2.5  PCB Stackup
        6. 7.9.2.6  Placement
        7. 7.9.2.7  DDR3 Keepout Region
        8. 7.9.2.8  Bulk Bypass Capacitors
        9. 7.9.2.9  High-Speed Bypass Capacitors
          1. 7.9.2.9.1 Return Current Bypass Capacitors
        10. 7.9.2.10 Net Classes
        11. 7.9.2.11 DDR3 Signal Termination
        12. 7.9.2.12 VTT
        13. 7.9.2.13 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.9.2.13.1 Three DDR3 Devices
            1. 7.9.2.13.1.1 CK and ADDR_CTRL Topologies, Three DDR3 Devices
            2. 7.9.2.13.1.2 CK and ADDR_CTRL Routing, Three DDR3 Devices
          2. 7.9.2.13.2 Two DDR3 Devices
            1. 7.9.2.13.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.9.2.13.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.9.2.13.3 One DDR3 Device
            1. 7.9.2.13.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.9.2.13.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        14. 7.9.2.14 Data Topologies and Routing Definition
          1. 7.9.2.14.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.9.2.14.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        15. 7.9.2.15 Routing Specification
          1. 7.9.2.15.1 CK and ADDR_CTRL Routing Specification
          2. 7.9.2.15.2 DQS and DQ Routing Specification
    10. 7.10 CVIDEO/SD-DAC Guidelines and Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
      1. 8.3.1 FCC Warning
      2. 8.3.2 Information About Cautions and Warnings
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Community Resources
    6. 8.6 Trademarks
      1. 8.6.1 静电放电警告
    7. 8.7 出口管制提示
    8. 8.8 术语表
  9. 9Mechanical Packaging Information
    1. 9.1 Mechanical Data

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4.2 Pin Attributes

Table 4-1 describes the terminal characteristics and the signals multiplexed on each ball. The following list describes the table column headers:

  1. BALL NUMBER: Ball number(s) on the bottom side associated with each signal on the bottom.
  2. BALL NAME: Mechanical name from package device (name is taken from muxmode 0).
  3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 0).

    4. NOTE

    Table 4-1 does not take into account the subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.3, Signal Descriptions.

    NOTE

    In the Driver off mode, the buffer is configured in high-impedance.
  4. MUXMODE: Multiplexing mode number:
    1. MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily the default muxmode.

      2. NOTE

      The default mode is the mode at the release of the reset; also see the RESET REL. MUXMODE column.
    2. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only MUXMODE values which correspond to defined functions should be used.
    3. An empty box means Not Applicable.
  5. TYPE: Signal type and direction:
    • I = Input
    • O = Output
    • IO = Input or Output
    • D = Open drain
    • DS = Differential Signaling
    • A = Analog
    • PWR = Power
    • GND = Ground
    • CAP = LDO Capacitor
  6. BALL RESET STATE: The state of the terminal at power-on reset:
    • drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
    • drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
    • An empty box means Not Applicable
  7. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
    • drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated).
    • drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated).
    • drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated).
    • OFF: High-impedance
    • PD: High-impedance with an active pulldown resistor
    • PU: High-impedance with an active pullup resistor
    • An empty box means Not Applicable

    8. NOTE

    For more information on the CORE_PWRON_RET_RST reset signal and its reset sources, see the Power, Reset, and Clock Management / Reset Management Functional Description section of the Device TRM.
  8. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).

    9. An empty box means Not Applicable.

  9. IO VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).

    10. An empty box means Not Applicable.

  10. POWER: The voltage supply that powers the terminal IO buffers.

    11. An empty box means Not Applicable.

  11. HYS: Indicates if the input buffer is with hysteresis:
    • Yes: With hysteresis
    • No: Without hysteresis
    • An empty box: Not Applicable

    12. NOTE

    For more information, see the hysteresis values in Section 5.7, DC Electrical Characteristics.
  12. BUFFER TYPE: Drive strength of the associated output buffer.

    13. An empty box means Not Applicable.

    NOTE

    For programmable buffer strength:

    • The default value is given in Table 4-1.
    • A note describes all possible values according to the selected muxmode.
  13. PULL UP / DOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
    • PU: Internal pullup
    • PD: Internal pulldown
    • PU/PD: Internal pullup and pulldown
    • PUx/PDy: Programmable internal pullup and pulldown
    • PDy: Programmable internal pulldown
    • An empty box means No pull
  14. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or logic "1") when the peripheral pin function is not selected by any of the CTRL_CORE_PADx registers.
    • 0: Logic 0 driven on the peripheral's input signal port.
    • 1: Logic 1 driven on the peripheral's input signal port.
    • blank: Pin state driven on the peripheral's input signal port.

    15. NOTE

    Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the proper software configuration (Hi-Z mode is not an input signal).

    NOTE

    When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that pad’s behavior is undefined. This should be avoided.

Table 4-1 Pin Attributes(1)

BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] MUXMODE [4] TYPE [5] BALL RESET STATE [6] BALL RESET REL. STATE [7] BALL RESET REL. MUXMODE [8] I/O VOLTAGE VALUE [9] POWER [10] HYS [11] BUFFER TYPE [12] PULL UP/DOWN TYPE [13] DSIS [14]
M19 adc_in0 adc_in0 0 A OFF OFF 0 1.8 vdda_adc GPADC
M20 adc_in1 adc_in1 0 A OFF OFF 0 1.8 vdda_adc GPADC
M21 adc_in2 adc_in2 0 A OFF OFF 0 1.8 vdda_adc GPADC
M22 adc_in3 adc_in3 0 A OFF OFF 0 1.8 vdda_adc GPADC
N22 adc_in4 adc_in4 0 A OFF OFF 0 1.8 vdda_adc GPADC
N21 adc_in5 adc_in5 0 A OFF OFF 0 1.8 vdda_adc GPADC
P19 adc_in6 adc_in6 0 A OFF OFF 0 1.8 vdda_adc GPADC
P18 adc_in7 adc_in7 0 A OFF OFF 0 1.8 vdda_adc GPADC
P20 adc_vrefp adc_vrefp 0 A OFF OFF 0 1.8 vdda_adc GPADC
N15 cap_vddram_core1 cap_vddram_core1 CAP
M15 cap_vddram_core2 cap_vddram_core2 CAP
M14 cap_vddram_dspeve cap_vddram_dspeve CAP
A11 csi2_0_dx0 csi2_0_dx0 0 I OFF OFF 0 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
A12 csi2_0_dx1 csi2_0_dx1 0 I OFF OFF 0 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
A13 csi2_0_dx2 csi2_0_dx2 0 I OFF OFF 0 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
A15 csi2_0_dx3 csi2_0_dx3 0 I OFF OFF 0 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
A16 csi2_0_dx4 csi2_0_dx4 0 I OFF OFF 0 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
B11 csi2_0_dy0 csi2_0_dy0 0 I OFF OFF 0 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
B12 csi2_0_dy1 csi2_0_dy1 0 I OFF OFF 0 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
B13 csi2_0_dy2 csi2_0_dy2 0 I OFF OFF 0 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
B15 csi2_0_dy3 csi2_0_dy3 0 I OFF OFF 0 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
B16 csi2_0_dy4 csi2_0_dy4 0 I OFF OFF 0 1.8 vdda_csi Yes LVCMOS CSI2 PU/PD
T18 cvideo_rset cvideo_rset 0 A OFF OFF 0 1.8 vdda_dac AVDAC
T17 cvideo_tvout cvideo_tvout 0 A OFF OFF 0 1.8 vdda_dac AVDAC
P17 cvideo_vfb cvideo_vfb 0 A OFF OFF 0 1.8 vdda_dac AVDAC
N6 dcan1_rx dcan1_rx 0 IO PU PU 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
gpio4_10 14 IO
Driver off 15 I
N5 dcan1_tx dcan1_tx 0 IO PU PU 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
gpio4_9 14 IO
Driver off 15 I
F2 ddr1_casn ddr1_casn 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
G1 ddr1_ck ddr1_ck 0 O PD drive clk (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
AB13 ddr1_dqm_ecc ddr1_dqm_ecc 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AB10 ddr1_dqsn_ecc ddr1_dqsn_ecc 0 IO PU PU 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AA10 ddr1_dqs_ecc ddr1_dqs_ecc 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
G2 ddr1_nck ddr1_nck 0 O PD drive clk (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
F1 ddr1_rasn ddr1_rasn 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
N1 ddr1_rst ddr1_rst 0 O PD drive 0 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
E3 ddr1_wen ddr1_wen 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
U4 ddr1_a0 ddr1_a0 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
C1 ddr1_a1 ddr1_a1 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
D3 ddr1_a2 ddr1_a2 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
R4 ddr1_a3 ddr1_a3 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
T4 ddr1_a4 ddr1_a4 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
N3 ddr1_a5 ddr1_a5 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
T2 ddr1_a6 ddr1_a6 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
N2 ddr1_a7 ddr1_a7 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
T1 ddr1_a8 ddr1_a8 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
U1 ddr1_a9 ddr1_a9 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
D1 ddr1_a10 ddr1_a10 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
R3 ddr1_a11 ddr1_a11 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
U2 ddr1_a12 ddr1_a12 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
C3 ddr1_a13 ddr1_a13 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
R2 ddr1_a14 ddr1_a14 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
V1 ddr1_a15 ddr1_a15 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
B3 ddr1_ba0 ddr1_ba0 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
A3 ddr1_ba1 ddr1_ba1 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
D2 ddr1_ba2 ddr1_ba2 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
F3 ddr1_cke0 ddr1_cke0 0 O PD drive 0 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
B2 ddr1_csn0 ddr1_csn0 0 O PD drive 1 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr2 LVCMOS DDR PUx/PDy
AA6 ddr1_d0 ddr1_d0 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AA8 ddr1_d1 ddr1_d1 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
Y8 ddr1_d2 ddr1_d2 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AA7 ddr1_d3 ddr1_d3 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AB4 ddr1_d4 ddr1_d4 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
Y5 ddr1_d5 ddr1_d5 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AA4 ddr1_d6 ddr1_d6 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
Y6 ddr1_d7 ddr1_d7 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AA18 ddr1_d8 ddr1_d8 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
Y21 ddr1_d9 ddr1_d9 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
AA21 ddr1_d10 ddr1_d10 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
Y22 ddr1_d11 ddr1_d11 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
AA19 ddr1_d12 ddr1_d12 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
AB20 ddr1_d13 ddr1_d13 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
Y17 ddr1_d14 ddr1_d14 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
AB18 ddr1_d15 ddr1_d15 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
AA3 ddr1_d16 ddr1_d16 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AA2 ddr1_d17 ddr1_d17 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
Y3 ddr1_d18 ddr1_d18 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
V2 ddr1_d19 ddr1_d19 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
U3 ddr1_d20 ddr1_d20 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
V3 ddr1_d21 ddr1_d21 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
Y2 ddr1_d22 ddr1_d22 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
Y1 ddr1_d23 ddr1_d23 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
U21 ddr1_d24 ddr1_d24 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
T20 ddr1_d25 ddr1_d25 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
R21 ddr1_d26 ddr1_d26 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
U20 ddr1_d27 ddr1_d27 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
R22 ddr1_d28 ddr1_d28 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
V20 ddr1_d29 ddr1_d29 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
W22 ddr1_d30 ddr1_d30 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
U22 ddr1_d31 ddr1_d31 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
AB8 ddr1_dqm0 ddr1_dqm0 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
Y18 ddr1_dqm1 ddr1_dqm1 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
AB3 ddr1_dqm2 ddr1_dqm2 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
W21 ddr1_dqm3 ddr1_dqm3 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
AA5 ddr1_dqs0 ddr1_dqs0 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AA20 ddr1_dqs1 ddr1_dqs1 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
W1 ddr1_dqs2 ddr1_dqs2 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
T21 ddr1_dqs3 ddr1_dqs3 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
AB5 ddr1_dqsn0 ddr1_dqsn0 0 IO PU PU 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
Y20 ddr1_dqsn1 ddr1_dqsn1 0 IO PU PU 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
W2 ddr1_dqsn2 ddr1_dqsn2 0 IO PU PU 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
T22 ddr1_dqsn3 ddr1_dqsn3 0 IO PU PU 0 1.2/1.35/1.5/1.8 vdds_ddr3 LVCMOS DDR PUx/PDy
Y11 ddr1_ecc_d0 ddr1_ecc_d0 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AA12 ddr1_ecc_d1 ddr1_ecc_d1 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AA11 ddr1_ecc_d2 ddr1_ecc_d2 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
Y9 ddr1_ecc_d3 ddr1_ecc_d3 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AA13 ddr1_ecc_d4 ddr1_ecc_d4 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AB11 ddr1_ecc_d5 ddr1_ecc_d5 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AA9 ddr1_ecc_d6 ddr1_ecc_d6 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
AB9 ddr1_ecc_d7 ddr1_ecc_d7 0 IO PD PD 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
P2 ddr1_odt0 ddr1_odt0 0 O PD drive 0 (OFF) 0 1.2/1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR PUx/PDy
H1 emu0 emu0 0 IO PU PU 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
gpio4_28 14 IO
Driver off 15 I
H2 emu1 emu1 0 IO PU PU 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
gpio4_29 14 IO
Driver off 15 I
E8 gpmc_ad0 gpmc_ad0 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_rxd2 1 I 0
gpio1_14 14 IO
sysboot0 15 I
A7 gpmc_ad1 gpmc_ad1 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_rxd1 1 I 0
gpio1_15 14 IO
sysboot1 15 I
F8 gpmc_ad2 gpmc_ad2 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_rxd0 1 I 0
gpio1_16 14 IO
sysboot2 15 I
B7 gpmc_ad3 gpmc_ad3 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
qspi1_rtclk 1 I 0
gpio1_17 14 IO
sysboot3 15 I
A6 gpmc_ad4 gpmc_ad4 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
cam_strobe 1 O
gpio1_18 14 IO
sysboot4 15 I
F7 gpmc_ad5 gpmc_ad5 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
uart2_txd 2 O
timer6 3 IO
spi3_d1 4 IO 0
gpio1_19 14 IO
sysboot5
mcasp2_aclkx 		15 I
E7 gpmc_ad6 gpmc_ad6 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
uart2_rxd 2 I 1
timer5 3 IO
spi3_d0 4 IO 0
gpio1_20 14 IO
sysboot6
mcasp2_fsx 		15 I
C6 gpmc_ad7 gpmc_ad7 0 IO OFF OFF 0 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
cam_shutter 1 O
timer4 3 IO
spi3_sclk 4 IO 0
gpio1_21 14 IO
Driver off
mcasp2_ahclkx 		15 I
B6 gpmc_ad8 gpmc_ad8 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
timer7 3 IO
spi3_cs0 4 IO 1
gpio1_22 14 IO
sysboot8
mcasp2_aclkr 		15 I
A5 gpmc_ad9 gpmc_ad9 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
eCAP1_in_PWM1_out 3 IO 0
spi3_cs1 4 IO 1
gpio1_23 14 IO
sysboot9
mcasp2_fsr 		15 I
D6 gpmc_ad10 gpmc_ad10 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
timer2 3 IO
gpio1_24 14 IO
sysboot10
mcasp2_axr0 		15 I
C5 gpmc_ad11 gpmc_ad11 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
timer3 3 IO
gpio1_25 14 IO
sysboot11
mcasp2_axr1 		15 I
B5 gpmc_ad12 gpmc_ad12 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
gpio1_26 14 IO
sysboot12
mcasp2_axr2 		15 I
D7 gpmc_ad13 gpmc_ad13 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_rxc 1 I 0
gpio1_27 14 IO
sysboot13
mcasp2_axr3 		15 I
B4 gpmc_ad14 gpmc_ad14 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
spi2_cs1 4 IO 1
gpio1_28 14 IO
sysboot14
mcasp2_axr4 		15 I
A4 gpmc_ad15 gpmc_ad15 0 IO OFF OFF 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
spi2_cs0 4 IO 1
gpio1_29 14 IO
sysboot15
mcasp2_axr5 		15 I
F12 gpmc_advn_ale gpmc_advn_ale 0 O PD PD 0 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txd2 1 O
ehrpwm1_tripzone_input 4 IO 0
clkout1 5 O
dma_evt4 6 I
gpio1_3 14 IO
Driver off 15 I
D12 gpmc_ben0 gpmc_ben0 0 O PD PD 0 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txctl 1 O
ehrpwm1A 4 O
dma_evt2 6 I
gpio1_1 14 IO
Driver off 15 I
E12 gpmc_ben1 gpmc_ben1 0 O PD PD 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txd3 1 O
ehrpwm1B 4 O
dma_evt3 6 I
gpio1_2 14 IO
Driver off 15 I
C12 gpmc_clk gpmc_clk 0 IO PD PD 0 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 0
rgmii1_txc 1 O
clkout0 5 O
dma_evt1 6 I
gpio1_0 14 IO
Driver off 15 I
C10 gpmc_cs0 gpmc_cs0 0 O PU PU 0 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
rgmii1_rxctl 1 I 0
gpio1_6 14 IO
Driver off 15 I
E10 gpmc_cs1 gpmc_cs1 0 O PU PU 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
qspi1_cs0 1 IO 1
gpio1_7 14 IO
Driver off 15 I
D10 gpmc_cs2 gpmc_cs2 0 O PU PU 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
qspi1_d3 1 IO 0
gpio1_8 14 IO
Driver off 15 I
A9 gpmc_cs3 gpmc_cs3 0 O PU PU 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
qspi1_d2 1 IO 0
gpio1_9 14 IO
Driver off 15 I
B9 gpmc_cs4 gpmc_cs4 0 O PU PU 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
qspi1_d0 1 IO 0
gpio1_10 14 IO
Driver off 15 I
F10 gpmc_cs5 gpmc_cs5 0 O PU PU 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
qspi1_d1 1 IO 0
gpio1_11 14 IO
Driver off 15 I
C8 gpmc_cs6 gpmc_cs6 0 O PU PU 15 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
qspi1_sclk 1 O
gpio1_12 14 IO
Driver off 15 I
A10 gpmc_oen_ren gpmc_oen_ren 0 O PD PD 0 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txd1 1 O
ehrpwm1_synci 4 I 0
clkout2 5 O
gpio1_4 14 IO
Driver off 15 I
D8 gpmc_wait0 gpmc_wait0 0 I PU PU 0 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD 1
rgmii1_rxd3 1 I 0
qspi1_rtclk 2 I 0
dma_evt4 6 I
gpio1_13 14 IO
Driver off 15 I
B10 gpmc_wen gpmc_wen 0 O PD PD 0 1.8/3.3 vddshv2 Yes Dual Voltage LVCMOS PU/PD
rgmii1_txd0 1 O
ehrpwm1_synco 4 O
gpio1_5 14 IO
Driver off 15 I
L3 i2c1_scl i2c1_scl 0 IO OFF OFF 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS I2C PU
L4 i2c1_sda i2c1_sda 0 IO OFF OFF 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS I2C PU
L6 i2c2_scl i2c2_scl 0 IO OFF OFF 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS I2C PU
L5 i2c2_sda i2c2_sda 0 IO OFF OFF 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS I2C PU
W6 mcan_rx mcan_rx 0 IO PU PU 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 1
cam_nreset 1 IO
vin2a_vsync0 2 I
spi1_cs3 3 IO 1
uart3_txd 4 O
gpmc_cs7 5 O
vin1b_vsync1 7 I 0
gpio4_12 14 IO
Driver off 15 I
W7 mcan_tx mcan_tx 0 IO PU PU 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD 1
vin2a_de0 1 I
vin2a_hsync0 2 I
spi1_cs2 3 IO 1
uart3_rxd 4 I 1
gpmc_wait1 6 I 1
vin1b_hsync1 7 I 0
vin1b_de1 8 I 0
gpio4_11 14 IO
Driver off 15 I
B17 mdio_d mdio_d 0 IO PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 1
spi4_d0 4 IO 0
gpio3_18 14 IO
Driver off 15 I
B19 mdio_mclk mdio_mclk 0 O PU PU 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 1
spi4_d1 4 IO 0
gpio3_17 14 IO
Driver off 15 I
G5 nmin nmin 0 I PU PU 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 1
G3 porz porz 0 I OFF OFF 0 1.8/3.3 vddshv1 Yes IHHV1833 PU/PD
G4 resetn resetn 0 I PU PU 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
B18 rgmii0_rxc rgmii0_rxc 0 I PD PD 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 0
cam_strobe 3 O
mmc_clk 5 IO 1
gpio3_25 14 IO
Driver off 15 I
C18 rgmii0_rxctl rgmii0_rxctl 0 I PD PD 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 0
cam_shutter 3 O
mmc_cmd 5 IO 1
gpio3_26 14 IO
Driver off 15 I
C16 rgmii0_txc rgmii0_txc 0 O PD PD 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
cam_strobe 3 O
spi4_sclk 4 IO 0
mmc_clk 5 IO 1
gpio3_19 14 IO
Driver off 15 I
C17 rgmii0_txctl rgmii0_txctl 0 O PD PD 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
cam_shutter 3 O
spi4_cs0 4 IO 1
mmc_cmd 5 IO 1
gpio3_20 14 IO
Driver off 15 I
A20 rgmii0_rxd0 rgmii0_rxd0 0 I PD PD 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 0
mmc_dat3 5 IO 1
gpio3_30 14 IO
Driver off 15 I
C20 rgmii0_rxd1 rgmii0_rxd1 0 I PD PD 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 0
mmc_dat2 5 IO 1
gpio3_29 14 IO
Driver off 15 I
B20 rgmii0_rxd2 rgmii0_rxd2 0 I PD PD 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 0
mmc_dat1 5 IO 1
gpio3_28 14 IO
Driver off 15 I
A19 rgmii0_rxd3 rgmii0_rxd3 0 I PD PD 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD 0
mmc_dat0 5 IO 1
gpio3_27 14 IO
Driver off 15 I
F17 rgmii0_txd0 rgmii0_txd0 0 O PD PD 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
mmc_dat3 5 IO 1
gpio3_24 14 IO
Driver off 15 I
E17 rgmii0_txd1 rgmii0_txd1 0 O PD PD 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
mmc_dat2 5 IO 1
gpio3_23 14 IO
Driver off 15 I
D16 rgmii0_txd2 rgmii0_txd2 0 O PD PD 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
eCAP1_in_PWM1_out 3 IO 0
mmc_dat1 5 IO 1
gpio3_22 14 IO
Driver off 15 I
E16 rgmii0_txd3 rgmii0_txd3 0 O PD PD 15 1.8/3.3 vddshv4 Yes Dual Voltage LVCMOS PU/PD
mmc_dat0 5 IO 1
gpio3_21 14 IO
Driver off 15 I
F4 rstoutn rstoutn 0 O PD drive 1 (OFF) 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
J6 rtck rtck 0 O PU drive clk (OFF) 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
gpio4_27 14 IO
Driver off 15 I
M2 spi1_sclk spi1_sclk 0 IO PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
uart3_rxd 1 I 1
gpio4_0 14 IO
Driver off 15 I
L1 spi2_sclk spi2_sclk 0 IO PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
uart3_rxd 1 I 1
ehrpwm1A 2 O
timer3 3 IO
gpio4_5 14 IO
Driver off 15 I
R6 spi1_cs0 spi1_cs0 0 IO PU PU 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 1
uart3_txd 1 O
gpio4_3 14 IO
Driver off 15 I
R5 spi1_cs1 spi1_cs1 0 IO PU PU 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 1
spi3_cs1 1 IO 1
timer6 4 IO
ehrpwm1_tripzone_input 7 IO 0
gpio4_4 14 IO
Driver off 15 I
T5 spi1_d0 spi1_d0 0 IO OFF OFF 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
uart3_rtsn 1 O
gpio4_2 14 IO
Driver off 15 I
U6 spi1_d1 spi1_d1 0 IO OFF OFF 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
uart3_ctsn 1 I 1
gpio4_1 14 IO
Driver off 15 I
L2 spi2_cs0 spi2_cs0 0 IO PU PU 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 1
uart3_txd 1 O
ehrpwm1B 2 O
timer4 3 IO
gpio4_8 14 IO
Driver off 15 I
R7 spi2_d0 spi2_d0 0 IO OFF OFF 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
uart3_rtsn 1 O
timer1 3 IO
gpio4_7 14 IO
sysboot7 15 I
N4 spi2_d1 spi2_d1 0 IO OFF OFF 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD 0
uart3_ctsn 1 I 1
timer5 3 IO
eCAP1_in_PWM1_out 7 IO 0
gpio4_6 14 IO
Driver off 15 I
J2 tclk tclk 0 I PU PU 0 1.8/3.3 vddshv1 Yes IQ1833 PU/PD
J1 tdi tdi 0 I PU PU 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
gpio4_25 14 IO
Driver off 15 I
J4 tdo tdo 0 O PU PU 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
gpio4_26 14 IO
Driver off 15 I
J3 tms tms 0 IO OFF OFF 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
J5 trstn trstn 0 I PD PD 0 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
F14 uart1_ctsn uart1_ctsn 0 I PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
xref_clk1 1 I
uart3_rxd 2 I 1
gpmc_a16 3 O
spi4_sclk 4 IO 0
spi1_cs2 5 IO 1
timer3 6 IO
ehrpwm1_synci 7 I 0
clkout0 8 O
vin2a_hsync0 9 I
gpmc_a12 10 O
gpmc_clk 11 IO 0
dcan1_tx 12 IO
gpio4_15 14 IO
Driver off 15 I
C14 uart1_rtsn uart1_rtsn 0 O PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
uart3_txd 2 O
gpmc_a17 3 O
spi4_cs0 4 IO 1
spi1_cs3 5 IO 1
timer4 6 IO
ehrpwm1_synco 7 O
qspi1_rtclk 8 I 0
vin2a_vsync0 9 I
gpmc_a13 10 O
dcan1_rx 12 IO
gpio4_16 14 IO
Driver off 15 I
F13 uart1_rxd uart1_rxd 0 I PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
spi4_d1 4 IO 0
qspi1_rtclk 5 I 0
gpmc_a12 10 O
mcan_tx 12 IO 1
gpio4_13 14 IO
Driver off 15 I
E14 uart1_txd uart1_txd 0 O PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
spi4_d0 4 IO 0
gpmc_a13 10 O
mcan_rx 12 IO 1
gpio4_14 14 IO
Driver off 15 I
F15 uart2_ctsn uart2_ctsn 0 I OFF OFF 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
xref_clk1 2 I
gpmc_a18 3 O
spi3_sclk 4 IO 0
qspi1_cs1 5 IO 1
timer7 6 IO
vin2a_hsync0 9 I
gpmc_clk 10 IO 0
mcan_tx 12 IO 1
gpio4_19 14 IO
Driver off 15 I
F16 uart2_rtsn uart2_rtsn 0 O PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
eCAP1_in_PWM1_out 1 IO 0
gpmc_a19 3 O
spi3_cs0 4 IO 1
timer8 6 IO
vin2a_vsync0 9 I
mcan_rx 12 IO 1
gpio4_20 14 IO
Driver off 15 I
D14 uart2_rxd uart2_rxd 0 I PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD 1
spi3_d1 4 IO 0
timer1 6 IO
ehrpwm1A 7 O
gpmc_clk 10 IO 0
gpmc_a12 11 O
dcan1_tx 12 IO
gpio4_17 14 IO
Driver off 15 I
D15 uart2_txd uart2_txd 0 O PU PU 15 1.8/3.3 vddshv3 Yes Dual Voltage LVCMOS PU/PD
spi3_d0 4 IO 0
timer2 6 IO
ehrpwm1B 7 O
gpmc_a13 11 O
dcan1_rx 12 IO
gpio4_18 14 IO
Driver off 15 I
H12, H13, H7, J10, J11, J15, K12, L12, L15, N12, N16, P10, P14 vdd vdd PWR
P22 vdda_adc vdda_adc PWR
A14 vdda_csi vdda_csi PWR
U19 vdda_dac vdda_dac PWR
N8 vdda_ddr_dsp vdda_ddr_dsp PWR
M8 vdda_gmac_core vdda_gmac_core PWR
E21 vdda_osc vdda_osc PWR
H14 vdda_per vdda_per PWR
G12, J7, L16, P13, T11 vdds18v vdds18v PWR
P7, T9 vdds18v_ddr1 vdds18v_ddr1 PWR
G7 vdds18v_ddr2 vdds18v_ddr2 PWR
T16, V21 vdds18v_ddr3 vdds18v_ddr3 PWR
K2, K7, L7, M7 vddshv1 vddshv1 PWR
B8, G11, G8, G9 vddshv2 vddshv2 PWR
G14 vddshv3 vddshv3 PWR
A18, E20 vddshv4 vddshv4 PWR
H17, J16, J21 vddshv5 vddshv5 PWR
AA16, T10, T12, T13 vddshv6 vddshv6 PWR
AA1, AB6, R1, T7, T8 vdds_ddr1 vdds_ddr1 PWR
C2, E2, G6 vdds_ddr2 vdds_ddr2 PWR
AA22, AB19, T15 vdds_ddr3 vdds_ddr3 PWR
K8, L8, M9, P11, P12, P8, P9 vdd_dspeve vdd_dspeve PWR
F22 vin1a_clk0 vin1a_clk0 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_pclk 1 I 0
clkout0 4 O
gpio1_30 14 IO
Driver off
mcasp3_aclkx 		15 I
G18 vin1a_d0 vin1a_d0 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data2 1 I 0
gpio2_3 14 IO
Driver off
mcasp3_axr1 		15 I
G21 vin1a_d1 vin1a_d1 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data3 1 I 0
gpio2_4 14 IO
Driver off
mcasp3_axr2 		15 I
G22 vin1a_d2 vin1a_d2 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data4 1 I 0
gpio2_5 14 IO
Driver off
mcasp3_axr3 		15 I
H18 vin1a_d3 vin1a_d3 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data5 1 I 0
gpio2_6 14 IO
Driver off
mcasp3_axr4 		15 I
H20 vin1a_d4 vin1a_d4 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data6 1 I 0
gpio2_7 14 IO
Driver off
mcasp3_axr5 		15 I
H19 vin1a_d5 vin1a_d5 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data7 1 I 0
gpio2_8 14 IO
xref_clk2
mcasp3_ahclkx 		15 I
H22 vin1a_d6 vin1a_d6 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data8 1 I 0
gpio2_9 14 IO
Driver off
mcasp3_fsx 		15 I
H21 vin1a_d7 vin1a_d7 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data9 1 I 0
gpio2_10 14 IO
Driver off 15 I
J17 vin1a_d8 vin1a_d8 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data10 1 I 0
vin1b_d0 2 I 0
gpmc_a8 3 O
sys_nirq2 7 I
gpio2_11 14 IO
Driver off 15 I
K22 vin1a_d9 vin1a_d9 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data11 1 I 0
vin1b_d1 2 I 0
gpmc_a9 3 O
sys_nirq1 7 I
gpio2_12 14 IO
Driver off 15 I
K21 vin1a_d10 vin1a_d10 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data12 1 I 0
vin1b_d2 2 I 0
gpmc_a10 3 O
sys_nirq2 7 I
gpio2_13 14 IO
Driver off 15 I
K18 vin1a_d11 vin1a_d11 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data13 1 I 0
vin1b_d3 2 I 0
gpmc_a11 3 O
sys_nirq1 7 I
gpio2_14 14 IO
Driver off 15 I
K17 vin1a_d12 vin1a_d12 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data14 1 I 0
vin1b_d4 2 I 0
gpmc_a12 3 O
dma_evt1 6 I
gpio2_15 14 IO
Driver off 15 I
K19 vin1a_d13 vin1a_d13 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_wen 1 I 0
vin1b_d5 2 I 0
gpmc_a13 3 O
dma_evt2 6 I
gpio2_16 14 IO
Driver off 15 I
K20 vin1a_d14 vin1a_d14 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_fid 1 IO 0
vin1b_d6 2 I 0
gpmc_a14 3 O
gpio2_17 14 IO
Driver off 15 I
L21 vin1a_d15 vin1a_d15 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data15 1 I 0
vin1b_d7 2 I 0
gpmc_a15 3 O
gpio2_18 14 IO
Driver off 15 I
F21 vin1a_de0 vin1a_de0 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_hsync 1 IO 0
vin1b_clk1 2 I 0
clkout1 4 O
gpio1_31 14 IO
Driver off 15 I
F20 vin1a_fld0 vin1a_fld0 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_vsync 1 IO 0
vin2b_clk1 2 I 0
clkout2 4 O
gpio2_0 14 IO
Driver off
mcasp3_aclkr 		15 I
F19 vin1a_hsync0 vin1a_hsync0 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data0 1 I 0
vin1a_de0 2 I 0
gpio2_1 14 IO
Driver off
mcasp3_fsr 		15 I
G19 vin1a_vsync0 vin1a_vsync0 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD 0
cpi_data1 1 I 0
gpio2_2 14 IO
Driver off
mcasp3_axr0 		15 I
L22 vin2a_clk0 vin2a_clk0 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD
gpio2_19 14 IO
Driver off 15 I
M17 vin2a_de0 vin2a_de0 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD
cam_strobe 1 O
vin2b_hsync1 2 I 0
vin2b_de1 5 I 0
gpio4_21 14 IO
Driver off 15 I
M18 vin2a_fld0 vin2a_fld0 0 I PD PD 15 1.8/3.3 vddshv5 Yes Dual Voltage LVCMOS PU/PD
cam_shutter 1 O
vin2b_vsync1 2 I 0
gpio4_22 14 IO
Driver off 15 I
AB17 vout1_clk vout1_clk 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
vin1a_d12 2 I 0
clkout0 4 O
vin2a_clk0 9 I
gpio2_20 14 IO
Driver off 15 I
U17 vout1_de vout1_de 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_aclkx 1 IO 0
vin1a_d13 2 I 0
clkout1 4 O
gpio2_21 14 IO
Driver off 15 I
W17 vout1_fld vout1_fld 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_fsx 1 IO 0
vin1a_d14 2 I 0
clkout2 4 O
gpio2_22 14 IO
Driver off 15 I
AA17 vout1_hsync vout1_hsync 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_aclkr 1 IO 0
vin1a_d15 2 I 0
vin2a_de0 9 I
gpio2_23 14 IO
Driver off 15 I
U16 vout1_vsync vout1_vsync 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_fsr 1 IO 0
vin2a_fld0 9 I
gpio2_24 14 IO
Driver off 15 I
W16 vout1_d0 vout1_d0 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr0 1 IO 0
mmc_clk 5 IO 1
gpio2_25 14 IO
Driver off 15 I
V16 vout1_d1 vout1_d1 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr1 1 IO 0
mmc_cmd 5 IO 1
gpio2_26 14 IO
Driver off 15 I
U15 vout1_d2 vout1_d2 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr2 1 IO 0
mcasp1_axr8 4 IO 0
mmc_dat0 5 IO 1
gpio2_27 14 IO
Driver off 15 I
V15 vout1_d3 vout1_d3 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr3 1 IO 0
mcasp1_axr9 4 IO 0
mmc_dat1 5 IO 1
gpio2_28 14 IO
Driver off 15 I
Y15 vout1_d4 vout1_d4 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr4 1 IO 0
mcasp1_axr10 4 IO 0
mmc_dat2 5 IO 1
gpio2_29 14 IO
Driver off 15 I
W15 vout1_d5 vout1_d5 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr5 1 IO 0
mcasp1_axr11 4 IO 0
mmc_dat3 5 IO 1
vin2a_clk0 9 I
gpio2_30 14 IO
Driver off 15 I
AA15 vout1_d6 vout1_d6 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr6 1 IO 0
mcasp1_axr12 4 IO 0
emu2 6 O
vin2a_de0 9 I
gpio2_31 14 IO
Driver off 15 I
AB15 vout1_d7 vout1_d7 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr7 1 IO 0
eCAP1_in_PWM1_out 3 IO 0
mcasp1_axr13 4 IO 0
emu3 6 O
vin2a_fld0 9 I
gpio3_0 14 IO
Driver off 15 I
AA14 vout1_d8 vout1_d8 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr8 1 IO 0
vin2a_d0 2 I 0
gpmc_a20 3 O
emu4 6 O
gpio3_1 14 IO
Driver off 15 I
AB14 vout1_d9 vout1_d9 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr9 1 IO 0
vin2a_d1 2 I 0
gpmc_a21 3 O
emu5 6 O
gpio3_2 14 IO
Driver off 15 I
U13 vout1_d10 vout1_d10 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr10 1 IO 0
vin2a_d2 2 I 0
gpmc_a22 3 O
emu6 6 O
gpio3_3 14 IO
Driver off 15 I
V13 vout1_d11 vout1_d11 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr11 1 IO 0
vin2a_d3 2 I 0
gpmc_a23 3 O
emu7 6 O
gpio3_4 14 IO
Driver off 15 I
Y13 vout1_d12 vout1_d12 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr12 1 IO 0
vin2a_d4 2 I 0
gpmc_a24 3 O
emu8 6 O
gpio3_5 14 IO
Driver off
mcasp2_ahclkx 		15 I
W13 vout1_d13 vout1_d13 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr13 1 IO 0
vin2a_d5 2 I 0
gpmc_a25 3 O
emu9 6 O
gpio3_6 14 IO
Driver off
mcasp2_aclkr 		15 I
U11 vout1_d14 vout1_d14 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr14 1 IO 0
vin2a_d6 2 I 0
gpmc_a26 3 O
emu10 6 O
gpio3_7 14 IO
Driver off
mcasp2_aclkx 		15 I
V11 vout1_d15 vout1_d15 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_axr15 1 IO 0
vin2a_d7 2 I 0
gpmc_a27 3 O
emu11 6 O
gpio3_8 14 IO
Driver off
mcasp2_fsx 		15 I
U9 vout1_d16 vout1_d16 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
mcasp1_ahclkx 1 O
vin2a_d8 2 I 0
gpmc_a0 3 O
mcasp1_axr8 4 IO 0
vin2b_d0 5 I 0
emu12 6 O
gpio3_9 14 IO
Driver off 15 I
W11 vout1_d17 vout1_d17 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
vin2a_d9 2 I 0
gpmc_a1 3 O
mcasp1_axr9 4 IO 0
vin2b_d1 5 I 0
emu13 6 O
gpio3_10 14 IO
Driver off
mcasp2_fsr 		15 I
V9 vout1_d18 vout1_d18 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
vin2a_d10 2 I 0
gpmc_a2 3 O
mcasp1_axr10 4 IO 0
vin2b_d2 5 I 0
emu14 6 O
gpio3_11 14 IO
Driver off
mcasp2_axr0 		15 I
W9 vout1_d19 vout1_d19 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
vin2a_d11 2 I 0
gpmc_a3 3 O
mcasp1_axr11 4 IO 0
vin2b_d3 5 I 0
emu15 6 O
gpio3_12 14 IO
Driver off
mcasp2_axr1 		15 I
U8 vout1_d20 vout1_d20 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
vin2a_d12 2 I 0
gpmc_a4 3 O
mcasp1_axr12 4 IO 0
vin2b_d4 5 I 0
emu16 6 O
gpio3_13 14 IO
Driver off
mcasp2_axr2 		15 I
W8 vout1_d21 vout1_d21 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
vin2a_d13 2 I 0
gpmc_a5 3 O
mcasp1_axr13 4 IO 0
vin2b_d5 5 I 0
emu17 6 O
gpio3_14 14 IO
Driver off
mcasp2_axr3 		15 I
U7 vout1_d22 vout1_d22 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
vin2a_d14 2 I 0
gpmc_a6 3 O
mcasp1_axr14 4 IO 0
vin2b_d6 5 I 0
emu18 6 O
gpio3_15 14 IO
Driver off
mcasp2_axr4 		15 I
V7 vout1_d23 vout1_d23 0 O PD PD 15 1.8/3.3 vddshv6 Yes Dual Voltage LVCMOS PU/PD
vin2a_d15 2 I 0
gpmc_a7 3 O
mcasp1_axr15 4 IO 0
vin2b_d7 5 I 0
emu19 6 O
gpio3_16 14 IO
Driver off
mcasp2_axr5 		15 I
A1, A17, A22, A8, AB1, AB12, AB16, AB2, AB21, AB22, AB7, B22, E1, G10, G16, H10, H11, H15, H16, H8, H9, J22, K1, K10, K11, K13, K14, K15, K16, K9, M10, M11, M12, M13, M16, N10, N7, P1, P15, P16, R12, R16, R9, T14, V22 vss vss GND
P21 vssa_adc vssa_adc GND
B14 vssa_csi vssa_csi GND
T19 vssa_dac vssa_dac GND
D21 vssa_osc0 vssa_osc0 GND
C22 vssa_osc1 vssa_osc1 GND
E22 xi_osc0 xi_osc0 0 I 0 1.8 vdda_osc Yes LVCMOS Alog PD
B21 xi_osc1 xi_osc1 0 I 0 1.8 vdda_osc Yes LVCMOS Alog PD
D22 xo_osc0 xo_osc0 0 O 0 1.8 vdda_osc Yes LVCMOS Alog PD
C21 xo_osc1 xo_osc1 0 A 0 1.8 vdda_osc Yes LVCMOS Alog PD
M1 xref_clk0 xref_clk0 0 I PD PD 15 1.8/3.3 vddshv1 Yes Dual Voltage LVCMOS PU/PD
clkout0 1 O
spi3_cs0 4 IO 1
spi2_cs1 5 IO 1
spi1_cs0 6 IO 1
spi1_cs1 7 IO 1
gpio3_31 14 IO
Driver off 15 I
  1. NA in this table stands for Not Applicable.
  2. For more information on recommended operating conditions, see , Recommended Operating Conditions.
  3. The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.
  4. The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the Device TRM.
  5. In PUx / PDy, x and y = 60 to 300 μA.
    The output impedance settings (or drive strengths) of this IO are programmable (60 Ω, 80 Ω, 120 Ω) depending on the values of the I[2:0] registers.
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