6.4 IPU
The Imaging Processor Unit (IPU) subsystem contains twoArm® Cortex-M4 cores (IPU_C0 and IPU_C1) that share a common level 1 (L1) cache (called unicache). The two Cortex-M4 cores are completely homogeneous to one another. Any task possible using one Cortex-M4 core is also possible using the other Cortex-M4 core. Both Cortex-M4 cores could be used for tasks such as running RTOS, controlling ISP, SIMCOP, DSS, and other functions. It is software responsibility to distribute the various tasks between the Cortex-M4 cores for optimal performance. The integrated interrupt handling of the IPU subsystem allows it to function as an efficient control unit.
IPU is the boot master of this device with its own boot ROM.
The key features of the IPU subsystem are:
- Two Arm Cortex-M4 microprocessors (IPU_C0 and IPU_C1):
- Armv7-M and Thumb®-2 instruction set architecture (ISA)
- Armv6 SIMD and digital signal processor (DSP) extensions
- Single-cycle MAC
- Integrated nested vector interrupt controller (NVIC) (also called IPU_Cx_INTC, where x = 0, 1)
- Integrated bus matrix:
- Bus arbiter
- Bit-banding – atomic bit manipulation
- Write buffer
- Memory interface (I and D) plus system interface (S) and private peripheral bus (PPB)
- Registers:
- Thirteen general-purpose 32-bit registers
- Link register (LR)
- Program counter (PC)
- Program status register, xPSR
- Two banked SP registers
- Integrated power management
- Extensive debug capabilities
- Unicache interface:
- AHBLite to unicache interface
- Instruction and data interface
- Supports interleaved Cortex-M4 requests
- L1 cache (IPU_UNICACHE):
- 32KiB divided into 16 banks
- 4-way
- Runs at twice the Cortex-M4 CPU frequency
- Cache configuration lock/freeze/preload
- Internal MMU:
- 16-entry region-based address translation
- Read/write control and access type control
- Runs at twice the Cortex-M4 CPU frequency
- Execute Never (XN) MMU protection policy
- Little-endian format
- OCP port for configuration and cache maintenance
- Subsystem counter timer module (SCTM) connected to unicache
- L2 master interface (MIF):
- Splitter for access to memory or OCP ports
- Interleaved bank request for fast memory access
- L2 internal memories:
- 16KiB ROM – IPU_ROM; used for device boot/initialization
- 64KiB banked RAM – IPU_RAM
- L2 MMU (IPU_MMU): 32 entries with Table Walking Logic (TWL)
- Wake-up generator (IPU_WUGEN): Generates wake-up request from external interrupts
- Two OCP ports at IPU boundary (connected to the L3_MAIN interconnect):
- Master port – allows the IPU to access system resources (memories and peripherals)
- Slave port – allows other requestors to access a part of the IPU internal memory space
- Power management:
- Local power-management control: Configurable through the IPU_WUGEN registers.
- Two sleep modes supported by Cortex-M4, controlled by its integrated interrupt controller (NVIC).
- Cortex-M4 system is clock-gated in both sleep modes.
- NVIC interrupt interface stays awake.
- Supports L1 cache and L2 memories retention.
- Error-Correcting Code (ECC) supported for both L1 unicache and L2 RAM
- Debug/emulation features supported
For more information, see chapter Dual Cortex-M4 IPU Subsystem of the device TRM.