ZHCSG69E
November 2016 – May 2018
DM505
PRODUCTION DATA.
1
器件概述
1.1
特性
1.2
应用
1.3
说明
1.4
功能框图
2
修订历史记录
3
Device Comparison
3.1
Device Comparison Table
4
Terminal Configuration and Functions
4.1
Pin Diagram
4.2
Pin Attributes
4.3
Signal Descriptions
4.3.1
VIP
4.3.2
DSS
4.3.3
SD_DAC
4.3.4
ADC
4.3.5
Camera Control
4.3.6
CPI
4.3.7
CSI2
4.3.8
EMIF
4.3.9
GPMC
4.3.10
Timers
4.3.11
I2C
4.3.12
UART
4.3.13
McSPI
4.3.14
QSPI
4.3.15
McASP
4.3.16
DCAN and MCAN
4.3.17
GMAC_SW
4.3.18
SDIO Controller
4.3.19
GPIO
4.3.20
ePWM
4.3.21
Emulation and Debug Subsystem
4.3.22
System and Miscellaneous
4.3.22.1
Sysboot
4.3.22.2
Power, Reset and Clock Management (PRCM)
4.3.22.3
Enhanced Direct Memory Access (EDMA)
4.3.22.4
Interrupt Controllers (INTC)
4.3.23
Power Supplies
4.4
Pin Multiplexing
4.5
Connections for Unused Pins
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Power on Hour (POH) Limits
5.4
Recommended Operating Conditions
5.5
Operating Performance Points
5.5.1
AVS Requirements
5.5.2
Voltage And Core Clock Specifications
5.5.3
Maximum Supported Frequency
5.6
Power Consumption Summary
5.7
Electrical Characteristics
Table 5-6
LVCMOS DDR DC Electrical Characteristics
Table 5-7
Dual Voltage LVCMOS I2C DC Electrical Characteristics
Table 5-8
IQ1833 Buffers DC Electrical Characteristics
Table 5-9
IHHV1833 Buffers DC Electrical Characteristics
Table 5-10
LVCMOS Analog OSC Buffers DC Electrical Characteristics
Table 5-11
LVCMOS CSI2 DC Electrical Characteristics
Table 5-12
Dual Voltage LVCMOS DC Electrical Characteristics
Table 5-13
Analog-to-Digital ADC Subsystem Electrical Specifications
5.8
Thermal Characteristics
5.8.1
Package Thermal Characteristics
5.9
Timing Requirements and Switching Characteristics
5.9.1
Timing Parameters and Information
5.9.1.1
Parameter Information
5.9.1.1.1
1.8V and 3.3V Signal Transition Levels
5.9.1.1.2
1.8V and 3.3V Signal Transition Rates
5.9.1.1.3
Timing Parameters and Board Routing Analysis
5.9.2
Interface Clock Specifications
5.9.2.1
Interface Clock Terminology
5.9.2.2
Interface Clock Frequency
5.9.3
Power Supply Sequences
5.9.4
Clock Specifications
5.9.4.1
Input Clocks / Oscillators
5.9.4.1.1
OSC0 External Crystal
5.9.4.1.2
OSC0 Input Clock
5.9.4.1.3
Auxiliary Oscillator OSC1 Input Clock
5.9.4.1.3.1
OSC1 External Crystal
5.9.4.1.3.2
OSC1 Input Clock
5.9.4.1.4
RC On-die Oscillator Clock
5.9.4.2
Output Clocks
5.9.4.3
DPLLs, DLLs
5.9.4.3.1
DPLL Characteristics
5.9.4.3.2
DLL Characteristics
5.9.4.3.2.1
DPLL and DLL Noise Isolation
5.9.5
Recommended Clock and Control Signal Transition Behavior
5.9.6
Peripherals
5.9.6.1
Timing Test Conditions
5.9.6.2
VIP
5.9.6.3
DSS
5.9.6.4
ISS
5.9.6.4.1
CSI-2 MIPI D-PHY—1.5 V and 1.8 V
5.9.6.5
EMIF
5.9.6.6
GPMC
5.9.6.6.1
GPMC/NOR Flash Interface Synchronous Timing
5.9.6.6.2
GPMC/NOR Flash Interface Asynchronous Timing
5.9.6.6.3
GPMC/NAND Flash Interface Asynchronous Timing
5.9.6.7
GP Timers
5.9.6.7.1
GP Timer Features
5.9.6.8
I2C
Table 5-41
Timing Requirements for I2C Input Timings
Table 5-42
Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
5.9.6.9
UART
Table 5-43
Timing Requirements for UART
Table 5-44
Switching Characteristics Over Recommended Operating Conditions for UART
5.9.6.10
McSPI
5.9.6.11
QSPI
5.9.6.12
McASP
Table 5-52
Timing Requirements for McASP1
Table 5-53
Timing Requirements for McASP2
Table 5-54
Timing Requirements for McASP3
Table 5-55
Switching Characteristics Over Recommended Operating Conditions for McASP1
Table 5-56
Switching Characteristics Over Recommended Operating Conditions for McASP2
Table 5-57
Switching Characteristics Over Recommended Operating Conditions for McASP3
5.9.6.13
DCAN and MCAN
5.9.6.13.1
DCAN
5.9.6.13.2
MCAN
Table 5-60
Timing Requirements for CAN Receive
Table 5-61
Switching Characteristics Over Recommended Operating Conditions for CAN Transmit
5.9.6.14
GMAC_SW
5.9.6.14.1
GMAC MDIO Interface Timings
5.9.6.14.2
GMAC RGMII Timings
Table 5-65
Timing Requirements for rgmiin_rxc - RGMIIn Operation
Table 5-66
Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
Table 5-67
Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
Table 5-68
Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
5.9.6.15
SDIO Controller
5.9.6.15.1
MMC, SD Default Speed
5.9.6.15.2
MMC, SD High Speed
5.9.6.15.3
MMC, SD and SDIO SDR12 Mode
5.9.6.15.4
MMC, SD SDR25 Mode
5.9.6.16
GPIO
5.9.7
Emulation and Debug Subsystem
5.9.7.1
JTAG Electrical Data/Timing
Table 5-79
Timing Requirements for IEEE 1149.1 JTAG
Table 5-80
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
Table 5-81
Timing Requirements for IEEE 1149.1 JTAG With RTCK
Table 5-82
Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
5.9.7.2
Trace Port Interface Unit (TPIU)
5.9.7.2.1
TPIU PLL DDR Mode
6
Detailed Description
6.1
Description
6.2
Functional Block Diagram
6.3
DSP Subsystem
6.4
IPU
6.5
EVE
6.6
Memory Subsystem
6.6.1
EMIF
6.6.2
GPMC
6.6.3
ELM
6.6.4
OCMC
6.7
Interprocessor Communication
6.7.1
Mailbox
6.7.2
Spinlock
6.8
Interrupt Controller
6.9
EDMA
6.10
Peripherals
6.10.1
VIP
6.10.2
DSS
6.10.3
ADC
6.10.4
ISS
6.10.5
Timers
6.10.5.1
General-Purpose Timers
6.10.5.2
32-kHz Synchronized Timer (COUNTER_32K)
6.10.6
I2C
6.10.7
UART
6.10.7.1
UART Features
6.10.8
McSPI
6.10.9
QSPI
6.10.10
McASP
6.10.11
DCAN
6.10.12
MCAN
6.10.13
GMAC_SW
6.10.14
SDIO
6.10.15
GPIO
6.10.16
ePWM
6.10.17
eCAP
6.10.18
eQEP
6.11
On-Chip Debug
7
Applications, Implementation, and Layout
7.1
Introduction
7.1.1
Initial Requirements and Guidelines
7.2
Power Optimizations
7.2.1
Step 1: PCB Stack-up
7.2.2
Step 2: Physical Placement
7.2.3
Step 3: Static Analysis
7.2.3.1
PDN Resistance and IR Drop
7.2.4
Step 4: Frequency Analysis
7.2.5
System ESD Generic Guidelines
7.2.5.1
System ESD Generic PCB Guideline
7.2.5.2
Miscellaneous EMC Guidelines to Mitigate ESD Immunity
7.2.5.3
ESD Protection System Design Consideration
7.2.6
EMI / EMC Issues Prevention
7.2.6.1
Signal Bandwidth
7.2.6.2
Signal Routing
7.2.6.2.1
Signal Routing—Sensitive Signals and Shielding
7.2.6.2.2
Signal Routing—Outer Layer Routing
7.2.6.3
Ground Guidelines
7.2.6.3.1
PCB Outer Layers
7.2.6.3.2
Metallic Frames
7.2.6.3.3
Connectors
7.2.6.3.4
Guard Ring on PCB Edges
7.2.6.3.5
Analog and Digital Ground
7.3
Core Power Domains
7.3.1
General Constraints and Theory
7.3.2
Voltage Decoupling
7.3.3
Static PDN Analysis
7.3.4
Dynamic PDN Analysis
7.3.5
Power Supply Mapping
7.3.6
DPLL Voltage Requirement
7.3.7
Loss of Input Power Event
7.3.8
Example PCB Design
7.3.8.1
Example Stack-up
7.3.8.2
vdd_dspeve Example Analysis
7.4
Single-Ended Interfaces
7.4.1
General Routing Guidelines
7.4.2
QSPI Board Design and Layout Guidelines
7.4.2.1
If QSPI is operated in Mode 0 (POL=0, PHA=0):
7.4.2.2
If QSPI is operated in Mode 3 (POL=1, PHA=1):
7.5
Differential Interfaces
7.5.1
General Routing Guidelines
7.5.2
CSI2 Board Design and Routing Guidelines
7.5.2.1
CSI2_0 MIPI CSI-2 (1.5 Gbps)
7.5.2.1.1
General Guidelines
7.5.2.1.2
Length Mismatch Guidelines
7.5.2.1.2.1
CSI2_0 MIPI CSI-2 (1.5 Gbps)
7.5.2.1.3
Frequency-domain Specification Guidelines
7.6
Clock Routing Guidelines
7.6.1
Oscillator Ground Connection
7.7
LPDDR2 Board Design and Layout Guidelines
7.7.1
LPDDR2 Board Designs
7.7.2
LPDDR2 Device Configurations
7.7.3
LPDDR2 Interface
7.7.3.1
LPDDR2 Interface Schematic
7.7.3.2
Compatible JEDEC LPDDR2 Devices
7.7.3.3
LPDDR2 PCB Stackup
7.7.3.4
LPDDR2 Placement
7.7.3.5
LPDDR2 Keepout Region
7.7.3.6
LPDDR2 Net Classes
7.7.3.7
LPDDR2 Signal Termination
7.7.3.8
LPDDR2 DDR_VREF Routing
7.7.4
Routing Specification
7.7.4.1
DQS[x] and DQ[x] Routing Specification
7.7.4.2
CK and ADDR_CTRL Routing Specification
7.8
DDR2 Board Design and Layout Guidelines
7.8.1
DDR2 General Board Layout Guidelines
7.8.2
DDR2 Board Design and Layout Guidelines
7.8.2.1
Board Designs
7.8.2.2
DDR2 Interface
7.8.2.2.1
DDR2 Interface Schematic
7.8.2.2.2
Compatible JEDEC DDR2 Devices
7.8.2.2.3
PCB Stackup
7.8.2.2.4
Placement
7.8.2.2.5
DDR2 Keepout Region
7.8.2.2.6
Bulk Bypass Capacitors
7.8.2.2.7
High-Speed Bypass Capacitors
7.8.2.2.8
Net Classes
7.8.2.2.9
DDR2 Signal Termination
7.8.2.2.10
VREF Routing
7.8.2.3
DDR2 CK and ADDR_CTRL Routing
7.9
DDR3 Board Design and Layout Guidelines
7.9.1
DDR3 General Board Layout Guidelines
7.9.2
DDR3 Board Design and Layout Guidelines
7.9.2.1
Board Designs
7.9.2.2
DDR3 Device Combinations
7.9.2.3
DDR3 Interface Schematic
7.9.2.3.1
32-Bit DDR3 Interface
7.9.2.3.2
16-Bit DDR3 Interface
7.9.2.4
Compatible JEDEC DDR3 Devices
7.9.2.5
PCB Stackup
7.9.2.6
Placement
7.9.2.7
DDR3 Keepout Region
7.9.2.8
Bulk Bypass Capacitors
7.9.2.9
High-Speed Bypass Capacitors
7.9.2.9.1
Return Current Bypass Capacitors
7.9.2.10
Net Classes
7.9.2.11
DDR3 Signal Termination
7.9.2.12
VTT
7.9.2.13
CK and ADDR_CTRL Topologies and Routing Definition
7.9.2.13.1
Three DDR3 Devices
7.9.2.13.1.1
CK and ADDR_CTRL Topologies, Three DDR3 Devices
7.9.2.13.1.2
CK and ADDR_CTRL Routing, Three DDR3 Devices
7.9.2.13.2
Two DDR3 Devices
7.9.2.13.2.1
CK and ADDR_CTRL Topologies, Two DDR3 Devices
7.9.2.13.2.2
CK and ADDR_CTRL Routing, Two DDR3 Devices
7.9.2.13.3
One DDR3 Device
7.9.2.13.3.1
CK and ADDR_CTRL Topologies, One DDR3 Device
7.9.2.13.3.2
CK and ADDR/CTRL Routing, One DDR3 Device
7.9.2.14
Data Topologies and Routing Definition
7.9.2.14.1
DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
7.9.2.14.2
DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
7.9.2.15
Routing Specification
7.9.2.15.1
CK and ADDR_CTRL Routing Specification
7.9.2.15.2
DQS and DQ Routing Specification
7.10
CVIDEO/SD-DAC Guidelines and Electrical Data/Timing
8
Device and Documentation Support
8.1
Device Nomenclature
8.1.1
Standard Package Symbolization
8.1.2
Device Naming Convention
8.2
Tools and Software
8.3
Documentation Support
8.3.1
FCC Warning
8.3.2
Information About Cautions and Warnings
8.4
Receiving Notification of Documentation Updates
8.5
Community Resources
8.6
Trademarks
8.6.1
静电放电警告
8.7
出口管制提示
8.8
术语表
9
Mechanical Packaging Information
9.1
Mechanical Data
封装选项
机械数据 (封装 | 引脚)
ABF|367
MPBGAJ4B
散热焊盘机械数据 (封装 | 引脚)
订购信息
zhcsg69e_oa
7.7.4
Routing Specification
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