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ZHCSG69E November 2016 – May 2018 DM505

PRODUCTION DATA.

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ABF|367
- MPBGAJ4B

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7.8.2.3 DDR2 CK and ADDR_CTRL Routing

Figure 7-43 shows the topology of the routing for the CK and ADDR_CTRL net classes. The route is a point to point connection with required skew matching.

Figure 7-43 CK and ADDR_CTRL Routing and Topology

Table 7-32 CK and ADDR_CTRL Routing Specification

NO.	PARAMETER	MIN	MAX	UNIT
RSC21	Center-to-center ddrx_ck - ddrx_nck spacing		2w
RSC22	ddrx_ck / ddrx_nck skew		5	ps
RSC25	Center-to-center CK to other DDR2 trace spacing^⁽²⁾	4w
RSC26	CK/ADDR_CTRL trace length^⁽³⁾		680	ps
RSC27	ADDR_CTRL-to-CK skew mismatch		25	ps
RSC28	ADDR_CTRL-to-ADDR_CTRL skew mismatch		25	ps
RSC29	Center-to-center ADDR_CTRL to other DDR2 trace spacing^⁽²⁾	4w
RSC210	Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing^⁽²⁾	3w

Series terminator, if used, should be located closest to the Device.
Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing congestion.
This is the longest routing length of the CK and ADDR_CTRL net classes.

Figure 7-44 shows the topology and routing for the DQS and DQ net classes; the routes are point to point. Skew matching across bytes is not needed nor recommended. The termination resistor should be placed near the processor.

Figure 7-44 DQS and DQ Routing and Topology

Table 7-33 DQS and DQ Routing Specification

NO.	PARAMETER	MIN	MAX	UNIT
RSDQ21	Center-to-center DQS-DQSn spacing in E0\|E1\|E2\|E3	2w
RSDQ22	DQS-DQSn skew in E0\|E1\|E2\|E3		5	ps
RSDQ23	Center-to-center DQS to other DDR2 trace spacing^⁽¹⁾	4w
RSDQ24	DQS/DQ trace length ^{⁽²⁾⁽³⁾⁽⁴⁾}		325	ps
RSDQ25	DQ-to-DQS skew mismatch^{⁽²⁾⁽³⁾⁽⁴⁾}		10	ps
RSDQ26	DQ-to-DQ skew mismatch^{⁽²⁾⁽³⁾⁽⁴⁾}		10	ps
RSDQ27	DQ-to-DQ/DQS via count mismatch^{⁽²⁾⁽³⁾⁽⁴⁾}		1	Vias
RSDQ28	Center-to-center DQ to other DDR2 trace spacing^{⁽¹⁾⁽⁵⁾}	4w
RSDQ29	Center-to-center DQ to other DQ trace spacing^{⁽¹⁾⁽⁶⁾⁽⁷⁾}	3w
RSDQ210	DQ/DQS E skew mismatch^{⁽²⁾⁽³⁾⁽⁴⁾}		25	ps

Center-to-center spacing is allowed to fall to minimum 2w for up to 500 mils of routed length to accommodate BGA escape and routing congestion.
A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated DQS (2 DQSs) per DDR EMIF used.
A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS (4 DQSs) per DDR EMIF used.
There is no need, and it is not recommended, to skew match across data bytes; that is, from DQS0 and data byte 0 to DQS1 and data byte1.
DQs from other DQS domains are considered other DDR2 trace.
DQs from other data bytes are considered other DDR2 trace.
This is the longest routing distance of each of the DQS and DQ net classes.