7.9.1 DDR3 General Board Layout Guidelines

To help ensure good signaling performance, consider the following board design guidelines:

• Avoid crossing splits in the power plane.
• Use the widest trace that is practical between decoupling capacitors and memory module.
• Maintain a single reference
• Minimize ISI by keeping impedances matched.
• Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.
• Keep the stub length as short as possible.
• Add additional spacing for on-clock and strobe nets to eliminate crosstalk.
• Maintain a common ground reference for all bypass and decoupling capacitors.
• Take into account the differences in propagation delays between microstrip and stripline nets when evaluating timing constraints.