ZHCSG69E November   2016  – May 2018 DM505

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Device Comparison Table
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  SD_DAC
      4. 4.3.4  ADC
      5. 4.3.5  Camera Control
      6. 4.3.6  CPI
      7. 4.3.7  CSI2
      8. 4.3.8  EMIF
      9. 4.3.9  GPMC
      10. 4.3.10 Timers
      11. 4.3.11 I2C
      12. 4.3.12 UART
      13. 4.3.13 McSPI
      14. 4.3.14 QSPI
      15. 4.3.15 McASP
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 SDIO Controller
      19. 4.3.19 GPIO
      20. 4.3.20 ePWM
      21. 4.3.21 Emulation and Debug Subsystem
      22. 4.3.22 System and Miscellaneous
        1. 4.3.22.1 Sysboot
        2. 4.3.22.2 Power, Reset and Clock Management (PRCM)
        3. 4.3.22.3 Enhanced Direct Memory Access (EDMA)
        4. 4.3.22.4 Interrupt Controllers (INTC)
      23. 4.3.23 Power Supplies
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. Table 5-6   LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7   Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8   IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9   IHHV1833 Buffers DC Electrical Characteristics
      5. Table 5-10 LVCMOS Analog OSC Buffers DC Electrical Characteristics
      6. Table 5-11 LVCMOS CSI2 DC Electrical Characteristics
      7. Table 5-12 Dual Voltage LVCMOS DC Electrical Characteristics
      8. Table 5-13 Analog-to-Digital ADC Subsystem Electrical Specifications
    8. 5.8 Thermal Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Timing Requirements and Switching Characteristics
      1. 5.9.1 Timing Parameters and Information
        1. 5.9.1.1 Parameter Information
          1. 5.9.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.9.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.9.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.9.2 Interface Clock Specifications
        1. 5.9.2.1 Interface Clock Terminology
        2. 5.9.2.2 Interface Clock Frequency
      3. 5.9.3 Power Supply Sequences
      4. 5.9.4 Clock Specifications
        1. 5.9.4.1 Input Clocks / Oscillators
          1. 5.9.4.1.1 OSC0 External Crystal
          2. 5.9.4.1.2 OSC0 Input Clock
          3. 5.9.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.9.4.1.3.1 OSC1 External Crystal
            2. 5.9.4.1.3.2 OSC1 Input Clock
          4. 5.9.4.1.4 RC On-die Oscillator Clock
        2. 5.9.4.2 Output Clocks
        3. 5.9.4.3 DPLLs, DLLs
          1. 5.9.4.3.1 DPLL Characteristics
          2. 5.9.4.3.2 DLL Characteristics
            1. 5.9.4.3.2.1 DPLL and DLL Noise Isolation
      5. 5.9.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.9.6 Peripherals
        1. 5.9.6.1  Timing Test Conditions
        2. 5.9.6.2  VIP
        3. 5.9.6.3  DSS
        4. 5.9.6.4  ISS
          1. 5.9.6.4.1 CSI-2 MIPI D-PHY—1.5 V and 1.8 V
        5. 5.9.6.5  EMIF
        6. 5.9.6.6  GPMC
          1. 5.9.6.6.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.9.6.6.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.9.6.6.3 GPMC/NAND Flash Interface Asynchronous Timing
        7. 5.9.6.7  GP Timers
          1. 5.9.6.7.1 GP Timer Features
        8. 5.9.6.8  I2C
          1. Table 5-41 Timing Requirements for I2C Input Timings
          2. Table 5-42 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        9. 5.9.6.9  UART
          1. Table 5-43 Timing Requirements for UART
          2. Table 5-44 Switching Characteristics Over Recommended Operating Conditions for UART
        10. 5.9.6.10 McSPI
        11. 5.9.6.11 QSPI
        12. 5.9.6.12 McASP
          1. Table 5-52 Timing Requirements for McASP1
          2. Table 5-53 Timing Requirements for McASP2
          3. Table 5-54 Timing Requirements for McASP3
          4. Table 5-55 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-56 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-57 Switching Characteristics Over Recommended Operating Conditions for McASP3
        13. 5.9.6.13 DCAN and MCAN
          1. 5.9.6.13.1  DCAN
          2. 5.9.6.13.2  MCAN
          3. Table 5-60 Timing Requirements for CAN Receive
          4. Table 5-61 Switching Characteristics Over Recommended Operating Conditions for CAN Transmit
        14. 5.9.6.14 GMAC_SW
          1. 5.9.6.14.1 GMAC MDIO Interface Timings
          2. 5.9.6.14.2 GMAC RGMII Timings
            1. Table 5-65 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-66 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-67 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-68 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        15. 5.9.6.15 SDIO Controller
          1. 5.9.6.15.1 MMC, SD Default Speed
          2. 5.9.6.15.2 MMC, SD High Speed
          3. 5.9.6.15.3 MMC, SD and SDIO SDR12 Mode
          4. 5.9.6.15.4 MMC, SD SDR25 Mode
        16. 5.9.6.16 GPIO
      7. 5.9.7 Emulation and Debug Subsystem
        1. 5.9.7.1 JTAG Electrical Data/Timing
          1. Table 5-79 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 5-80 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 5-81 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 5-82 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.9.7.2 Trace Port Interface Unit (TPIU)
          1. 5.9.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  DSP Subsystem
    4. 6.4  IPU
    5. 6.5  EVE
    6. 6.6  Memory Subsystem
      1. 6.6.1 EMIF
      2. 6.6.2 GPMC
      3. 6.6.3 ELM
      4. 6.6.4 OCMC
    7. 6.7  Interprocessor Communication
      1. 6.7.1 Mailbox
      2. 6.7.2 Spinlock
    8. 6.8  Interrupt Controller
    9. 6.9  EDMA
    10. 6.10 Peripherals
      1. 6.10.1  VIP
      2. 6.10.2  DSS
      3. 6.10.3  ADC
      4. 6.10.4  ISS
      5. 6.10.5  Timers
        1. 6.10.5.1 General-Purpose Timers
        2. 6.10.5.2 32-kHz Synchronized Timer (COUNTER_32K)
      6. 6.10.6  I2C
      7. 6.10.7  UART
        1. 6.10.7.1 UART Features
      8. 6.10.8  McSPI
      9. 6.10.9  QSPI
      10. 6.10.10 McASP
      11. 6.10.11 DCAN
      12. 6.10.12 MCAN
      13. 6.10.13 GMAC_SW
      14. 6.10.14 SDIO
      15. 6.10.15 GPIO
      16. 6.10.16 ePWM
      17. 6.10.17 eCAP
      18. 6.10.18 eQEP
    11. 6.11 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1  Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2  Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
        3. 7.2.5.3 ESD Protection System Design Consideration
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3  Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_dspeve Example Analysis
    4. 7.4  Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
        1. 7.4.2.1 If QSPI is operated in Mode 0 (POL=0, PHA=0):
        2. 7.4.2.2 If QSPI is operated in Mode 3 (POL=1, PHA=1):
    5. 7.5  Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 CSI2 Board Design and Routing Guidelines
        1. 7.5.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          1. 7.5.2.1.1 General Guidelines
          2. 7.5.2.1.2 Length Mismatch Guidelines
            1. 7.5.2.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
          3. 7.5.2.1.3 Frequency-domain Specification Guidelines
    6. 7.6  Clock Routing Guidelines
      1. 7.6.1 Oscillator Ground Connection
    7. 7.7  LPDDR2 Board Design and Layout Guidelines
      1. 7.7.1 LPDDR2 Board Designs
      2. 7.7.2 LPDDR2 Device Configurations
      3. 7.7.3 LPDDR2 Interface
        1. 7.7.3.1 LPDDR2 Interface Schematic
        2. 7.7.3.2 Compatible JEDEC LPDDR2 Devices
        3. 7.7.3.3 LPDDR2 PCB Stackup
        4. 7.7.3.4 LPDDR2 Placement
        5. 7.7.3.5 LPDDR2 Keepout Region
        6. 7.7.3.6 LPDDR2 Net Classes
        7. 7.7.3.7 LPDDR2 Signal Termination
        8. 7.7.3.8 LPDDR2 DDR_VREF Routing
      4. 7.7.4 Routing Specification
        1. 7.7.4.1 DQS[x] and DQ[x] Routing Specification
        2. 7.7.4.2 CK and ADDR_CTRL Routing Specification
    8. 7.8  DDR2 Board Design and Layout Guidelines
      1. 7.8.1 DDR2 General Board Layout Guidelines
      2. 7.8.2 DDR2 Board Design and Layout Guidelines
        1. 7.8.2.1 Board Designs
        2. 7.8.2.2 DDR2 Interface
          1. 7.8.2.2.1  DDR2 Interface Schematic
          2. 7.8.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.8.2.2.3  PCB Stackup
          4. 7.8.2.2.4  Placement
          5. 7.8.2.2.5  DDR2 Keepout Region
          6. 7.8.2.2.6  Bulk Bypass Capacitors
          7. 7.8.2.2.7  High-Speed Bypass Capacitors
          8. 7.8.2.2.8  Net Classes
          9. 7.8.2.2.9  DDR2 Signal Termination
          10. 7.8.2.2.10 VREF Routing
        3. 7.8.2.3 DDR2 CK and ADDR_CTRL Routing
    9. 7.9  DDR3 Board Design and Layout Guidelines
      1. 7.9.1 DDR3 General Board Layout Guidelines
      2. 7.9.2 DDR3 Board Design and Layout Guidelines
        1. 7.9.2.1  Board Designs
        2. 7.9.2.2  DDR3 Device Combinations
        3. 7.9.2.3  DDR3 Interface Schematic
          1. 7.9.2.3.1 32-Bit DDR3 Interface
          2. 7.9.2.3.2 16-Bit DDR3 Interface
        4. 7.9.2.4  Compatible JEDEC DDR3 Devices
        5. 7.9.2.5  PCB Stackup
        6. 7.9.2.6  Placement
        7. 7.9.2.7  DDR3 Keepout Region
        8. 7.9.2.8  Bulk Bypass Capacitors
        9. 7.9.2.9  High-Speed Bypass Capacitors
          1. 7.9.2.9.1 Return Current Bypass Capacitors
        10. 7.9.2.10 Net Classes
        11. 7.9.2.11 DDR3 Signal Termination
        12. 7.9.2.12 VTT
        13. 7.9.2.13 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.9.2.13.1 Three DDR3 Devices
            1. 7.9.2.13.1.1 CK and ADDR_CTRL Topologies, Three DDR3 Devices
            2. 7.9.2.13.1.2 CK and ADDR_CTRL Routing, Three DDR3 Devices
          2. 7.9.2.13.2 Two DDR3 Devices
            1. 7.9.2.13.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.9.2.13.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.9.2.13.3 One DDR3 Device
            1. 7.9.2.13.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.9.2.13.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        14. 7.9.2.14 Data Topologies and Routing Definition
          1. 7.9.2.14.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.9.2.14.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        15. 7.9.2.15 Routing Specification
          1. 7.9.2.15.1 CK and ADDR_CTRL Routing Specification
          2. 7.9.2.15.2 DQS and DQ Routing Specification
    10. 7.10 CVIDEO/SD-DAC Guidelines and Electrical Data/Timing
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
      1. 8.3.1 FCC Warning
      2. 8.3.2 Information About Cautions and Warnings
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Community Resources
    6. 8.6 Trademarks
      1. 8.6.1 静电放电警告
    7. 8.7 出口管制提示
    8. 8.8 术语表
  9. 9Mechanical Packaging Information
    1. 9.1 Mechanical Data

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

4.3.15 McASP

NOTE

For more information, see the Serial Communication Interface / Multichannel Audio Serial Port (McASP) section of the Device TRM.

CAUTION

The IO timings provided in Section 5.9, Timing Requirements and Switching Characteristics are only valid if signals within a single IOSET are used. The IOSETs are defined in Table 5-58.

Table 4-16 McASP Signal Descriptions

SIGNAL NAME DESCRIPTION TYPE BALL
Multichannel Audio Serial Port 1
mcasp1_axr0 McASP1 Transmit/Receive Data IO W16
mcasp1_axr1 McASP1 Transmit/Receive Data IO V16
mcasp1_axr2 McASP1 Transmit/Receive Data IO U15
mcasp1_axr3 McASP1 Transmit/Receive Data IO V15
mcasp1_axr4 McASP1 Transmit/Receive Data IO Y15
mcasp1_axr5 McASP1 Transmit/Receive Data IO W15
mcasp1_axr6 McASP1 Transmit/Receive Data IO AA15
mcasp1_axr7 McASP1 Transmit/Receive Data IO AB15
mcasp1_axr8 McASP1 Transmit/Receive Data IO AA14,U15,U9
mcasp1_axr9 McASP1 Transmit/Receive Data IO AB14,V15,W11
mcasp1_axr10 McASP1 Transmit/Receive Data IO U13,V9,Y15
mcasp1_axr11 McASP1 Transmit/Receive Data IO V13,W15,W9
mcasp1_axr12 McASP1 Transmit/Receive Data IO AA15,U8,Y13
mcasp1_axr13 McASP1 Transmit/Receive Data IO AB15,W13,W8
mcasp1_axr14 McASP1 Transmit/Receive Data IO U11,U7
mcasp1_axr15 McASP1 Transmit/Receive Data IO V11,V7
mcasp1_fsx McASP1 Transmit Frame Sync IO W17
mcasp1_aclkr McASP1 Receive Bit Clock IO AA17
mcasp1_fsr McASP1 Receive Frame Sync IO U16
mcasp1_ahclkx McASP1 Transmit High-Frequency Master Clock O U9
mcasp1_aclkx McASP1 Transmit Bit Clock IO U17
Multichannel Audio Serial Port 2
mcasp2_axr0 McASP2 Transmit/Receive Data IO D6, V9
mcasp2_axr1 McASP2 Transmit/Receive Data IO C5, W9
mcasp2_axr2 McASP2 Transmit/Receive Data IO B5, U8
mcasp2_axr3 McASP2 Transmit/Receive Data IO D7, W8
mcasp2_axr4 McASP2 Transmit/Receive Data IO B4, U7
mcasp2_axr5 McASP2 Transmit/Receive Data IO A4, V7
mcasp2_fsx McASP2 Transmit Frame Sync IO E7, V11
mcasp2_aclkr McASP2 Receive Bit Clock IO B6, W13
mcasp2_fsr McASP2 Receive Frame Sync IO A5, W11
mcasp2_ahclkx McASP2 Transmit High-Frequency Master Clock O C6, Y13
mcasp2_aclkx McASP2 Transmit Bit Clock IO F7, U11
Multichannel Audio Serial Port 3
mcasp3_axr0 McASP3 Transmit/Receive Data IO G19
mcasp3_axr1 McASP3 Transmit/Receive Data IO G18
mcasp3_axr2 McASP3 Transmit/Receive Data IO G21
mcasp3_axr3 McASP3 Transmit/Receive Data IO G22
mcasp3_axr4 McASP3 Transmit/Receive Data IO H18
mcasp3_axr5 McASP3 Transmit/Receive Data IO H20
mcasp3_fsx McASP3 Transmit Frame Sync IO H22
mcasp3_ahclkx McASP3 Transmit High-Frequency Master Clock O H19
mcasp3_aclkx McASP3 Transmit Bit Clock IO F22
mcasp3_aclkr McASP3 Receive Bit Clock IO F20
mcasp3_fsr McASP3 Receive Frame Sync IO F19
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